Texas Instruments SM320C6455-EP manual EDMA3 Device-Specific Information

SM320C6455-EP

FIXED-POINT DIGITAL SIGNAL PROCESSOR

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SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008

7.4.1EDMA3 Device-Specific Information

The EDMA supports two addressing modes: constant addressing and increment addressing mode. Constant addressing mode is applicable to a very limited set of use cases; for most applications increment mode can be used. On the C6455 DSP, the EDMA can use constant addressing mode only with the Enhanced Viterbi-Decoder Coprocessor (VCP2) and the Enhanced Turbo Decoder Coprocessor (TCP2). Constant addressing mode is not supported by any other peripheral or internal memory in the C6455 DSP. Note that increment mode is supported by all C6455 peripherals, including VCP2 and TCP2. For more information on these two addressing modes, see the TMS320C645x DSP Enhanced DMA (EDMA3) Controller User's Guide (literature number SPRU966).

A DSP interrupt must be generated at the end of an HPI or PCI boot operation to begin execution of the loaded application. Since the DSP interrupt generated by the HPI and PCI is mapped to the EDMA event DSP_EVT (DMA channel 0), it will get recorded in bit 0 of the EDMA Event Register (ER). This event must be cleared by software before triggering transfers on DMA channel 0. The EDMA3 on the C6455 DSP supports active memory protection, but it does not support proxied memory protection.

7.4.2EDMA3 Channel Synchronization Events

The EDMA3 supports up to 64 DMA channels that can be used to service system peripherals and to move data between system memories. DMA channels can be triggered by synchronization events generated by system peripherals. Table 7-3lists the source of the synchronization event associated with each of the DMA channels. On the C6455, the association of each synchronization event and DMA channel is fixed and cannot be reprogrammed.

For more detailed information on the EDMA3 module and how EDMA3 events are enabled, captured, processed, prioritized, linked, chained, and cleared, etc., see the TMS320C645x DSP Enhanced DMA (EDMA3) Controller User's Guide (literature number SPRU966).

Table 7-3. C6455 EDMA3 Channel Synchronization Events(1)

EDMA	BINARY	EVENT NAME	EVENT DESCRIPTION
CHANNEL
0(2)	000 0000	DSP_EVT	HPI/PCI-to-DSP event
1	000 0001	TEVTLO0	Timer 0 lower counter event
2	000 0010	TEVTHI0	Timer 0 high counter event
3	000 0011	-	None
4	000 0100	-	None
5	000 0101	-	None
6	000 0110	-	None
7	000 0111	-	None
8	000 1000	-	None
9	000 1001	-	None
10	000 1010	-	None
11	000 1011	-	None
12	000 1100	XEVT0	McBSP0 transmit event
13	000 1101	REVT0	McBSP0 receive event
14	000 1110	XEVT1	McBSP1 transmit event
15	000 1111	REVT1	McBSP1 receive event
16	001 0000	TEVTLO1	Timer 1 lower counter event
17	001 0001	TEVTHI1	Timer 1 high counter event

(1)In addition to the events shown in this table, each of the 64 channels also can be synchronized with the transfer completion or alternate transfer completion events. For more detailed information on EDMA event-transfer chaining, see the TMS320C645x DSP Enhanced DMA (EDMA3) Controller User's Guide (literature number SPRU966).

(2)HPI boot and PCI boot are terminated using a DSP interrupt. The DSP interrupt is registered in bit 0 (channel 0) of the EDMA Event Register (ER). This event must be cleared by software before triggering transfers on DMA channel 0.

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