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Texas Instruments SM320F2812-HT specifications Event Manager Modules EVA, EVB

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SGUS062A –JUNE 2009 –REVISED APRIL 2010

4.2Event Manager Modules (EVA, EVB)

The event-manager modules include general-purpose (GP) timers, full-compare/PWM units, capture units, and quadrature-encoder pulse (QEP) circuits. EVA and EVB timers, compare units, and capture units function identically. However, timer/unit names differ for EVA and EVB. Table 4-2shows the module and signal names used. Table 4-2shows the features and functionality available for the event-manager modules and highlights EVA nomenclature.

Event managers A and B have identical peripheral register sets with EVA starting at 7400h and EVB starting at 7500h. The paragraphs in this section describe the function of GP timers, compare units, capture units, and QEPs using EVA nomenclature. These paragraphs are applicable to EVB with regard to function— however, module/signal names would differ. Table 4-3lists the EVA registers. For more information, see the TMS320x281x DSP Event Manager (EV) Reference Guide (literature number SPRU065).

Table 4-2. Module and Signal Names for EVA and EVB

EVENT MANAGER MODULES

EVA

EVB

MODULE

SIGNAL

MODULE

SIGNAL

GP Timers

GP Timer 1

T1PWM/T1CMP

GP Timer 3

T3PWM/T3CMP

GP Timer 2

T2PWM/T2CMP

GP Timer 4

T4PWM/T4CMP

Compare 1

PWM1/2

Compare 4

PWM7/8

Compare Units

Compare 2

PWM3/4

Compare 5

PWM9/10

Compare 3

PWM5/6

Compare 6

PWM11/12

Capture 1

CAP1

Capture 4

CAP4

Capture Units

Capture 2

CAP2

Capture 5

CAP5

Capture 3

CAP3

Capture 6

CAP6

QEP1

QEP1

QEP3

QEP3

QEP Channels

QEP2

QEP4

QEP2

QEP4

QEPI1

QEPI2

External Clock Inputs

Direction

TDIRA

Direction

TDIRB

External Clock

TCLKINA

External Clock

TCLKINB

C1TRIP

C4TRIP

External Trip Inputs

Compare

C2TRIP

Compare

C5TRIP

C3TRIP

C6TRIP

T1CTRIP_PDPINTA

(1)

T3CTRIP_PDPINTB

External Trip Inputs

(1)

T4CTRIP/EVBSOC

T2CTRIP/EVASOC

(1)In the 24x/240x-compatible mode, the T1CTRIP_PDPINTA pin functions as PDPINTA and the T3CTRIP_PDPINTB pin functions as

PDPINTB.

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Texas Instruments SM320F2812-HT specifications Event Manager Modules EVA, EVB, Module and Signal Names for EVA and EVB

Contents

Data Manual SM320F2812-HT Contents Peripherals SM320F2812-HTSPI Slave Mode Timing List of Figures General-Purpose Input Timing List of Tables Interrupt Switching Characteristics 149 Copyright 2009-2010, Texas Instruments Incorporated Check for Samples SM320F2812-HT Digital Signal ProcessorSupports Extreme Temperature Applications Description IntroductionF2812 Hardware FeaturesFeature Device Summary55.0 x 64.0 μm Die LayoutDIE PAD Backside DIE Size DIE PAD Size Coordinates Thickness Finish PotentialSM320F2812 172-Pin HFG Cqfp Top View Pin AssignmentsPIN no DIE PAD Signal DescriptionsSignal Descriptions1 Center Description HFG Xintf SignalsCenter Description HFG Signal DescriptionsCenter Description HFG Jtag and Miscellaneous Signals TDI TrstTCK TMSCenter Description HFG ADC Analog Input Signals Center Description HFG Power Signals SM320F2812-HT Gpiob or EVB SignalsPeripheral PIN no DIE PAD Gpio DIE PAD no Gpioe or Interrupt Signals Signal HFG CenterGpiod or EVA Signals Gpiod or EVB SignalsGpiof or McBSP Signals Signal HFG Center Gpiof or can SignalsGpiof or XF CPU Output Signal GPIOG4 Scitxdb O Signal HFG Center Gpiog or SCI-B SignalsGPIOG5 Scirxdb Functional Overview F2812 Memory Map See Notes A. Through G Memory MapAddress Range Program and Data Space Addresses of Flash Sectors in F2812H0 Saram Wait StatesArea CommentsPeripheral Bus Brief Descriptions1 C28x CPU Memory Bus Harvard Bus Architecture7 L0, L1, H0 SARAMs Boot ROMExternal Interface Xintf FlashCode Security Module Disclaimer Boot Mode SelectionBoot Mode Selected GPIOF4 GPIOF12 GPIOF3 GPIOF2 SecurityOscillator and PLL Low-Power ModesPeripheral Interrupt Expansion PIE Block External Interrupts XINT1, XINT2, XINT13, XnmiControl Peripherals 18 32-Bit CPU Timers 0, 1Peripheral Frames 0, 1, 2 PFn General-Purpose Input/Output Gpio MultiplexerRegister Map Serial Port PeripheralsName Address Range Access TypePeripheral Frame 0 Registers1 Peripheral Frame 1 Registers1Peripheral Frame 2 Registers1 External Interface, Xintf Device Emulation RegistersDevice Emulation Registers XZCS7 XWE XRD XR/W Xready XMP/MC Xhold Xholda Xclkout XZCS0XZCS0AND1 XZCS1XZCS2 XZCS6 XZCS6AND7Xrevision Register Bit Definitions Xintf Configuration and Control Register MappingsTiming Registers Xrevision RegisterInterrupts Intm INT1 INT2 INT11 INT12CPU PIE Interrupts 11. PIE Configuration and Control Registers1 12. External Interrupts Registers External InterruptsSystem Control Clock and Reset Domains13. PLL, Clocking, Watchdog, and Low-Power Mode Registers1 14. Pllcr Register Bit Definitions OSC and PLL BlockExternal Reference Oscillator Clock Option PLL Mode Remarks SysclkoutLoss of Input Clock PLL-Based Clock ModuleWatchdog Block Oscclk Clkin Sysclkout Low-Power Modes Block16. F2812 Low-Power Modes ModePschpsc TCR.4 32-Bit CPU-Timers 0/1/2Tddrhtddr PrdhprdINT1 to INT12 C28x INT13 PIE TINT1 TINT0 CPU-TIMERINT14 XINT13 TINT2 CPU-Timers 0, 1, 2 Configuration and Control Registers Event Manager Modules EVA EVB Signal Module and Signal Names for EVA and EVBEvent Manager Modules EVA, EVB EVA Registers1 Event Manager a Functional Block Diagram See Note a Programmable Deadband Generator General-Purpose GP TimersDouble Update PWM Mode Full-Compare UnitsExternal ADC Start-of-Conversion PWM CharacteristicsCapture Unit Quadrature-Encoder Pulse QEP CircuitEnhanced Analog-to-Digital Converter ADC Module ADC Adcenclk HspclkMUX ADCINA0 ADCINA7Adcbgrefin ² ADCINA70ADCINB70 AdcloAdclo Adcbgrefin SM320F2812-HTAvddrefbg Avssrefbg ADC Registers1 Enhanced Controller Area Network eCAN Module SN65HVD23x UnitCan Bus ECAN Memory Map Register Name Address Can Registers Map1Multichannel Buffered Serial Port McBSP Module Where Clksrg source could be LSPCLK, CLKX, or CLKR.2Clkx TX FifoLspclk FSXData REGISTERS, RECEIVE, Transmit Name Address Type Reset Value DescriptionMcBSP Register Summary HEXFifo Mode Registers applicable only in Fifo mode Serial Communications Interface SCI Module SCI-B Registers1 SCI-A Registers1−−−−− 10. Serial Communications Interface SCI Module Block DiagramSerial Peripheral Interface SPI Module 10. SPI Registers1 −−−−− −−−−−Register Description 11. Gpio Mux Registers1 212. Gpio Data Registers1 PIN Software Development Tools Device and Development Support Tool NomenclatureHardware Development Tools Documentation Support SM320F2812-HT Value Unit Absolute Maximum RatingsParameter Test Conditions MIN TYP MAX Unit Electrical CharacteristicsRecommended Operating Conditions MIN NOM MAX UnitHours Die Junction Temperature CMode Test Conditions Vddaio Current Consumption GraphsDD Current Reduction mA Power Sequencing RequirementsReducing Current Consumption Peripheral ModuleRecommended Low-Dropout Regulators Signal Transition LevelsSupplier Part Number VOH 80% 20% VOL Timing Parameter SymbologyVIH 90% 10% VIL Test Load Circuit General Notes on Timing Parameters85 pF Clock Table and Nomenclature Clock Requirements and CharacteristicsDevice Clock Table Input Clock RequirementsPossible PLL Configuration Modes1 Output Clock CharacteristicsXclkin Timing Requirements PLL Bypassed or Enabled Xclkin Timing Requirements PLL Disabled1Reset XRS Timing Requirements1 Reset TimingGPIOF14 XF/XPLLDISXF/XPLLDIS XMP/MC Xclkout XRSXCLKIN/2 Xclkin Xclkout XRSXCLKIN/8 GPIOF14/XFXclkout = Sysclkout Low-Power Mode Wakeup Timing10. Idle Mode Switching Characteristics1 A0−A1511. Standby Mode Switching Characteristics1 Sysclkout Cycles Device Status Flushing Pipeline Wake−up SignalStandby XCLKOUT²Parameter MIN TYP MAX Unit 12. Halt Mode Switching Characteristics1PWM Timing Event Manager InterfaceMAX Unit 13. PWM Switching Characteristics114. Timer and Capture Unit Timing Requirements1 Parameter Test Conditions MINInterrupt Timing 17. Interrupt Switching CharacteristicsTxCTRIP, CxTRIP PDPINTx See Note B 19. General-Purpose Output Switching CharacteristicsGeneral-Purpose Input/Output Gpio Output Timing 18. Interrupt Timing RequirementsQualprd Sysclkout General-Purpose Input/Output Gpio Input TimingQualprd = 1 2 x Sysclkout cycles x Output From Qualifier 21. SPI Master Mode External Timing Clock Phase = 01 2 SPI Master Mode TimingGPIOxn Spisomi Master In Data Must Be Valid SpisimoSM320F2812-HT 22. SPI Master Mode External Timing Clock Phase = 11 2Spisomi Data Valid23. SPI Slave Mode External Timing Clock Phase = 01 2 SPI Slave Mode TimingSM320F2812-HT Spisimo Data Must Be Valid 24. SPI Slave Mode External Timing Clock Phase = 11 2SM320F2812-HT X2TIMING = 26. Xtiming Register Configuration Restrictions1External Interface Xintf Timing 27. Valid and Invalid Timing129. Valid and Invalid Timing when using Synchronous XREADY1 28. Xtiming Register Configuration Restrictions130. Xtiming Register Configuration Restrictions1 32. Asynchronous XREADY1 31. Xtiming Register Configuration Restrictions133. Xintf Clock Configurations Mode Sysclkout Xtimclk XclkoutXINTCNF2 Clkoff Xtimclk Clkmode 28. Relationship Between Xtimclk and SysclkoutXR/W Xintf Signal Alignment to XclkoutXZCS0AND1, XZCS2 XZCS6AND7 External Interface Read Timing35. External Memory Interface Read Timing Requirements1 XCLKOUT=XTIMCLK XCLKOUT= 1/2 XtimclkDout External Interface Write TimingLead Active XCLKOUT=XTIMCLKSM320F2812-HT Setup time, Xready Synch low before Xclkout high/low DIN WS Synch Active Lead TrailXREADYSynch XCLKOUT=XTIMCLK XCLKOUT= 1/2 Xtimclk XZCS0AND1, XZCS2 WS AsynchXREADYAsynch Parameter MIN MAX Unit 33. Write With Synchronous Xready Access 34. Write With Asynchronous Xready Access XWE, XRD XZCS6AND7 XR/W Xhold and XholdaXZCS2 XZCS6AND7 XHOLD/XHOLDA Timing44. XHOLD/XHOLDA Timing Requirements Xclkout = XTIMCLK1 2 XR/W XZCS0AND136. XHOLD/XHOLDA Timing Requirements Xclkout = 1/2 Xtimclk XHOLD/XHOLDA Timing Requirements Xclkout = 1/2 XtimclkADC Absolute Maximum Ratings On-Chip Analog-to-Digital Converter46. DC Specifications1 TYP ADC Operating MODE/CONDITIONS 47. AC Specifications148. Current Consumption1 MIN TYP MAXPwdnadc ADC Power-Up Control Bit TimingADCIN0 Pwdnbg PwdnrefDetailed Description Sequential Sampling Mode Single Channel Smode =Sample n + 50. Sequential Sampling Mode Timing1Clock Remarks AT 25-MHz ADC Simultaneous Sampling Mode Dual-Channel Smode =Definitions of Specifications and Terminology Clkg + Clksrg Multichannel Buffered Serial Port McBSP TimingMcBSP Transmit and Receive Timing 52. McBSP Timing Requirements1 2Dxena = 53. McBSP Switching Characteristics1 2M19 M16 M18M17 M18 M1, M11 M2, M12 M13Master Slave Unit MIN MAX McBSP as SPI Master or Slave TimingParameter Master Slave Unit MIN MAX M39 M49 M58 62. Flash Parameters at 150-MHz SYSCLKOUT1 63. Flash/OTP Access Timing1Flash Timing Recommended Operating ConditionsWAIT-STATE Random Wait STATE2 64. Minimum Required Wait-States at Different Frequencies250 Mechanical Data Orderable Device Package Type Pins Package Qty Eco Plan LeadSamples Page DSP Products ApplicationsRfid