Texas Instruments Understanding McBSP Timing for SPI Master and Slave Operation

SM320F2812-HT

www.ti.com SGUS062A –JUNE 2009 –REVISED APRIL 2010

Table 6-58. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)(1)

NO.			MASTER	SLAVE		UNIT
			MIN MAX	MIN	MAX
M49	tsu(DRV-CKXH)	Setup time, DR valid before CLKX high	P – 10	8P – 10		ns
M50	th(CKXH-DRV)	Hold time, DR valid after CLKX high	P – 10	8P – 10		ns
M51	tsu(FXL-CKXL)	Setup time, FSX low before CLKX low		8P + 10		ns
M52	tc(CKX)	Cycle time, CLKX	2P	16P		ns

(1)Not production tested.

Table 6-59. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)(1) (2)

NO.		PARAMETER	MASTER	SLAVE		UNIT
			MIN MAX	MIN	MAX
M43	th(CKXH-FXL)	Hold time, FSX low after CLKX high	2P			ns
M44	td(FXL-CKXL)	Delay time, FSX low to CLKX low	P			ns
M47	tdis(FXH-DXHZ)	Disable time, DX high impedance following last data bit from FSX	6	6P + 6		ns
		high
M48	td(FXL-DXV)	Delay time, FSX low to DX valid	6	4P + 6		ns

(1)Not production tested.

(2)2P = 1/CLKG

For all SPI slave modes, CLKX has to be minimum eight CLKG cycles. Also, CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1. With maximum LSPCLK speed of 75 MHz, CLKX maximum frequency is LSPCLK/16 , that is 4.5 MHz and P = 13.3 ns.

CLKX

FSX

DX

DR

LSB	M51	MSB			M52
M43		M44
M47	M48
Bit 0		Bit(n-1)	(n-2)	(n-3)	(n-4)
		M49	M50
Bit 0		Bit(n-1)	(n-2)	(n-3)	(n-4)

Figure 6-45. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1

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