Event Manager Interface | Texas Instruments SM320F2812-HT guide

SM320F2812-HT

SGUS062A –JUNE 2009 –REVISED APRIL 2010

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A.IDLE instruction is executed to put the device into HALT mode.

B.The PLL block responds to the HALT signal. SYSCLKOUT is held for another 32 cycles before the oscillator is turned off and the CLKIN to the core is stopped. This 32-cycle delay enables the CPU pipe and any other pending operations to flush perperly.

C.Clocks to the device are turned off and the internal oscillator and PLL are shut down. The device is now in HALT mode and consumes absolute minimum power.

D.When XNMI is friven active (negative edge triggered shown, as an example), the oscillator is turned on; but the PLL is not activiated.

E.When XNMI is deactiveted, it initiates the PLL lock sequence, which takes 131, 072 X1/XCLKIN cycles.

F.When CLKIN to the core is enabled, the device responds to the interrupt (if enabled), after a latency. The HALT mode is now exited.

G.Normal operation resumes.

H.XCLKOUT = SYSCLKOUT

Figure 6-15. HALT Wakeup Using XNMI

6.16 Event Manager Interface

6.16.1 PWM Timing

PWM refers to all PWM outputs on EVA and EVB.

104 Electrical SpecificationsCopyright © 2009–2010, Texas Instruments Incorporated

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Texas Instruments SM320F2812-HT specifications Event Manager Interface, PWM Timing

SM320F2812-HT specifications

The Texas Instruments SM320F2812-HT is a highly capable digital signal processor (DSP) specifically designed for high-performance and real-time applications in harsh environments. This part of the C2000 family of microcontrollers caters to applications in areas such as industrial automation, motor control, and power conversion, where reliability and durability under extreme temperature conditions are paramount.

One of the standout features of the SM320F2812-HT is its robust architecture based on a 32-bit fixed-point core. This allows for efficient execution of complex algorithms while maintaining a high processing speed. The processor operates at clock speeds of up to 150 MHz, enabling it to handle multiple tasks simultaneously with minimal latency.

The SM320F2812-HT boasts an impressive memory configuration that includes up to 128 KB of flash memory and 4 KB of RAM. The integrated memory supports efficient data handling and storage, making it ideal for demanding applications that require quick access to critical information. The device also features various peripherals, including analog-to-digital converters (ADCs), pulse width modulation (PWM) modules, and serial communication interfaces, which enhance its functionality in real-time processing and control tasks.

Furthermore, this DSP employs advanced control algorithms and supports various communication protocols, allowing it to interoperate seamlessly with other devices within a system. Its capabilities are further enhanced by Texas Instruments’ extensive development tools and software libraries, which enable developers to accelerate design cycles and improve overall efficiency.

With its high temperature rating, the SM320F2812-HT is designed to operate within a temperature range from -40°C to 125°C, making it particularly well-suited for use in automotive, aerospace, and other rugged environments where traditional components might fail. The high reliability and endurance of this microcontroller make it a preferred choice among engineers looking for durable solutions without compromising performance.

In summary, the Texas Instruments SM320F2812-HT represents a powerful blend of processing capabilities, memory architecture, and environmental resilience. Its features make it a go-to option for developers in search of a robust DSP for real-time applications, ensuring that it meets the rigorous demands of various industrial sectors while delivering consistent performance.

Contents

Data Manual SM320F2812-HT Contents SM320F2812-HT Peripherals SPI Slave Mode Timing List of Figures General-Purpose Input Timing List of Tables Interrupt Switching Characteristics 149 Copyright 2009-2010, Texas Instruments Incorporated Digital Signal Processor Check for Samples SM320F2812-HT Supports Extreme Temperature Applications Introduction Description Hardware Features FeatureDevice Summary F2812 Die Layout DIE PAD Backside DIE Size DIE PAD SizeCoordinates Thickness Finish Potential 55.0 x 64.0 μm Pin Assignments SM320F2812 172-Pin HFG Cqfp Top View Signal Descriptions Signal Descriptions1Center Description HFG Xintf Signals PIN no DIE PAD Signal Descriptions Center Description HFG Center Description HFG Jtag and Miscellaneous Signals Trst TCKTMS TDI Center Description HFG ADC Analog Input Signals Center Description HFG Power Signals Peripheral PIN no DIE PAD Gpio DIE PAD no Gpiob or EVB SignalsSM320F2812-HT Signal HFG Center Gpiod or EVA SignalsGpiod or EVB Signals Gpioe or Interrupt Signals Gpiof or XF CPU Output Signal Signal HFG Center Gpiof or can SignalsGpiof or McBSP Signals GPIOG5 Scirxdb Signal HFG Center Gpiog or SCI-B SignalsGPIOG4 Scitxdb O Functional Overview Memory Map F2812 Memory Map See Notes A. Through G Addresses of Flash Sectors in F2812 Address Range Program and Data Space Wait States AreaComments H0 Saram Brief Descriptions 1 C28x CPUMemory Bus Harvard Bus Architecture Peripheral Bus Boot ROM External Interface XintfFlash 7 L0, L1, H0 SARAMs Boot Mode Selection Boot Mode Selected GPIOF4 GPIOF12 GPIOF3 GPIOF2Security Code Security Module Disclaimer Low-Power Modes Peripheral Interrupt Expansion PIE BlockExternal Interrupts XINT1, XINT2, XINT13, Xnmi Oscillator and PLL 18 32-Bit CPU Timers 0, 1 Peripheral Frames 0, 1, 2 PFnGeneral-Purpose Input/Output Gpio Multiplexer Control Peripherals Serial Port Peripherals Register Map Access Type Peripheral Frame 0 Registers1Peripheral Frame 1 Registers1 Name Address Range Peripheral Frame 2 Registers1 Device Emulation Registers Device Emulation RegistersExternal Interface, Xintf XZCS0XZCS0AND1 XZCS1 XZCS2XZCS6 XZCS6AND7 XZCS7 XWE XRD XR/W Xready XMP/MC Xhold Xholda Xclkout Xintf Configuration and Control Register Mappings Timing RegistersXrevision Register Xrevision Register Bit Definitions Interrupts CPU PIE Interrupts INT1 INT2 INT11 INT12Intm 11. PIE Configuration and Control Registers1 External Interrupts 12. External Interrupts Registers Clock and Reset Domains System Control 13. PLL, Clocking, Watchdog, and Low-Power Mode Registers1 OSC and PLL Block 14. Pllcr Register Bit Definitions PLL Mode Remarks Sysclkout Loss of Input ClockPLL-Based Clock Module External Reference Oscillator Clock Option Watchdog Block Low-Power Modes Block 16. F2812 Low-Power ModesMode Oscclk Clkin Sysclkout 32-Bit CPU-Timers 0/1/2 TddrhtddrPrdhprd Pschpsc TCR.4 INT14 XINT13 TINT2 INT13 PIE TINT1 TINT0 CPU-TIMERINT1 to INT12 C28x CPU-Timers 0, 1, 2 Configuration and Control Registers Event Manager Modules EVA, EVB Module and Signal Names for EVA and EVBEvent Manager Modules EVA EVB Signal EVA Registers1 Event Manager a Functional Block Diagram See Note a General-Purpose GP Timers Double Update PWM ModeFull-Compare Units Programmable Deadband Generator PWM Characteristics Capture UnitQuadrature-Encoder Pulse QEP Circuit External ADC Start-of-Conversion Enhanced Analog-to-Digital Converter ADC Module Adcenclk Hspclk MUX ADCINA0ADCINA7 ADC ADCINA70 ADCINB70Adclo Adcbgrefin ² Avddrefbg Avssrefbg SM320F2812-HTAdclo Adcbgrefin ADC Registers1 Enhanced Controller Area Network eCAN Module Can Bus UnitSN65HVD23x ECAN Memory Map Can Registers Map1 Register Name Address Where Clksrg source could be LSPCLK, CLKX, or CLKR.2 Multichannel Buffered Serial Port McBSP Module TX Fifo LspclkFSX Clkx Name Address Type Reset Value Description McBSP Register SummaryHEX Data REGISTERS, RECEIVE, Transmit Fifo Mode Registers applicable only in Fifo mode Serial Communications Interface SCI Module SCI-A Registers1 SCI-B Registers1 10. Serial Communications Interface SCI Module Block Diagram −−−−− Serial Peripheral Interface SPI Module 10. SPI Registers1 −−−−− −−−−− 11. Gpio Mux Registers1 2 Register Description 12. Gpio Data Registers1 PIN Hardware Development Tools Device and Development Support Tool NomenclatureSoftware Development Tools Documentation Support SM320F2812-HT Absolute Maximum Ratings Value Unit Electrical Characteristics Recommended Operating ConditionsMIN NOM MAX Unit Parameter Test Conditions MIN TYP MAX Unit Die Junction Temperature C Hours Mode Test Conditions Current Consumption Graphs Vddaio Power Sequencing Requirements Reducing Current ConsumptionPeripheral Module DD Current Reduction mA Supplier Part Number Signal Transition LevelsRecommended Low-Dropout Regulators VIH 90% 10% VIL Timing Parameter SymbologyVOH 80% 20% VOL 85 pF General Notes on Timing ParametersTest Load Circuit Clock Requirements and Characteristics Device Clock TableInput Clock Requirements Clock Table and Nomenclature Output Clock Characteristics Xclkin Timing Requirements PLL Bypassed or EnabledXclkin Timing Requirements PLL Disabled1 Possible PLL Configuration Modes1 Reset Timing Reset XRS Timing Requirements1 XF/XPLLDIS GPIOF14 Xclkout XRS XF/XPLLDIS XMP/MC Xclkin Xclkout XRS XCLKIN/8GPIOF14/XF XCLKIN/2 Low-Power Mode Wakeup Timing 10. Idle Mode Switching Characteristics1A0−A15 Xclkout = Sysclkout 11. Standby Mode Switching Characteristics1 Device Status Flushing Pipeline Wake−up Signal StandbyXCLKOUT² Sysclkout Cycles 12. Halt Mode Switching Characteristics1 Event Manager Interface PWM Timing 13. PWM Switching Characteristics1 14. Timer and Capture Unit Timing Requirements1Parameter Test Conditions MIN MAX Unit 17. Interrupt Switching Characteristics Interrupt Timing 19. General-Purpose Output Switching Characteristics General-Purpose Input/Output Gpio Output Timing18. Interrupt Timing Requirements TxCTRIP, CxTRIP PDPINTx See Note B Qualprd = 1 2 x Sysclkout cycles x Output From Qualifier General-Purpose Input/Output Gpio Input TimingQualprd Sysclkout GPIOxn SPI Master Mode Timing21. SPI Master Mode External Timing Clock Phase = 01 2 Spisimo Spisomi Master In Data Must Be Valid 22. SPI Master Mode External Timing Clock Phase = 11 2 Data Valid Spisomi SPI Slave Mode Timing 23. SPI Slave Mode External Timing Clock Phase = 01 2 SM320F2812-HT 24. SPI Slave Mode External Timing Clock Phase = 11 2 Spisimo Data Must Be Valid SM320F2812-HT 26. Xtiming Register Configuration Restrictions1 External Interface Xintf Timing27. Valid and Invalid Timing1 X2TIMING = 30. Xtiming Register Configuration Restrictions1 28. Xtiming Register Configuration Restrictions129. Valid and Invalid Timing when using Synchronous XREADY1 31. Xtiming Register Configuration Restrictions1 33. Xintf Clock ConfigurationsMode Sysclkout Xtimclk Xclkout 32. Asynchronous XREADY1 28. Relationship Between Xtimclk and Sysclkout XINTCNF2 Clkoff Xtimclk Clkmode Xintf Signal Alignment to Xclkout XR/W External Interface Read Timing 35. External Memory Interface Read Timing Requirements1XCLKOUT=XTIMCLK XCLKOUT= 1/2 Xtimclk XZCS0AND1, XZCS2 XZCS6AND7 External Interface Write Timing Lead ActiveXCLKOUT=XTIMCLK Dout SM320F2812-HT Setup time, Xready Synch low before Xclkout high/low XREADYSynch WS Synch Active Lead TrailDIN XREADYAsynch WS AsynchXCLKOUT=XTIMCLK XCLKOUT= 1/2 Xtimclk XZCS0AND1, XZCS2 Parameter MIN MAX Unit 33. Write With Synchronous Xready Access 34. Write With Asynchronous Xready Access Xhold and Xholda XWE, XRD XZCS6AND7 XR/W XHOLD/XHOLDA Timing 44. XHOLD/XHOLDA Timing Requirements Xclkout = XTIMCLK1 2XR/W XZCS0AND1 XZCS2 XZCS6AND7 XHOLD/XHOLDA Timing Requirements Xclkout = 1/2 Xtimclk 36. XHOLD/XHOLDA Timing Requirements Xclkout = 1/2 Xtimclk On-Chip Analog-to-Digital Converter ADC Absolute Maximum Ratings 46. DC Specifications1 47. AC Specifications1 48. Current Consumption1MIN TYP MAX TYP ADC Operating MODE/CONDITIONS ADC Power-Up Control Bit Timing ADCIN0Pwdnbg Pwdnref Pwdnadc Sequential Sampling Mode Single Channel Smode = Detailed Description Clock Remarks 50. Sequential Sampling Mode Timing1Sample n + Simultaneous Sampling Mode Dual-Channel Smode = AT 25-MHz ADC Definitions of Specifications and Terminology Multichannel Buffered Serial Port McBSP Timing McBSP Transmit and Receive Timing52. McBSP Timing Requirements1 2 Clkg + Clksrg 53. McBSP Switching Characteristics1 2 Dxena = M16 M18 M17 M18M1, M11 M2, M12 M13 M19 Parameter Master Slave Unit MIN MAX McBSP as SPI Master or Slave TimingMaster Slave Unit MIN MAX M39 M49 M58 63. Flash/OTP Access Timing1 Flash TimingRecommended Operating Conditions 62. Flash Parameters at 150-MHz SYSCLKOUT1 250 64. Minimum Required Wait-States at Different FrequenciesWAIT-STATE Random Wait STATE2 Mechanical Data Samples Package Type Pins Package Qty Eco Plan LeadOrderable Device Page Rfid Products ApplicationsDSP