Texas Instruments SM320F2812-HT specifications

SM320F2812-HT

SGUS062A –JUNE 2009 –REVISED APRIL 2010 www.ti.com

Figure 4-11is a block diagram of the SPI in slave mode.

SPIFFENA							Receiver	Overrun
SPIFFTX.14
							Overrun Flag	INT ENA
RX FIFO registers							SPISTS.7
SPIRXBUF								SPICTL.4
RX FIFO _0
RX FIFO _1									SPIINT/SPIRXINT
−−−−−					RX FIFO Interrupt
								RX Interrupt
RX FIFO _15
								Logic
	16
SPIRXBUF							SPIFFOVF FLAG
Buffer Register
							SPIFFRX.15
									To CPU
	TX FIFO registers
		SPITXBUF
		TX FIFO _15						TX Interrupt
		−−−−−				TX FIFO Interrupt
								Logic
		TX FIFO _1							SPITXINT
		TX FIFO _0
								SPI INT
			16
							SPI INT FLAG	ENA
		SPITXBUF					SPISTS.6
	Buffer Register
16								SPICTL.0
			16
						M		M
SPIDAT								S
Data Register						S	SW1			SPISIMO
SPIDAT.15 − 0						M		M
						S	SW2	S
	Talk									SPISOMI
	SPICTL.1
										SPISTE†
	State Control
								Master/Slave
SPI Char SPICCR.3 − 0						S			SPICTL.2
	3	2	1	0
								SW3
						M		Clock	Clock
	SPI Bit Rate						S	Polarity	Phase
LSPCLK	SPIBRR.6 − 0						M	SPICCR.6	SPICTL.3	SPICLK
6	5	4	3	2	1	0

²SPISTE is driven low by the master for a slave device.

Figure 4-11. Serial Peripheral Interface Module Block Diagram (Slave Mode)

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