Texas Instruments SM320F2812-HT specifications M39

SM320F2812-HT

SGUS062A –JUNE 2009 –REVISED APRIL 2010 www.ti.com

Table 6-56. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)(1)

NO.			MASTER			SLAVE		UNIT
			MIN	MAX		MIN	MAX
M39	tsu(DRV-CKXH)	Setup time, DR valid before CLKX high	P – 10		8P	– 10		ns
M40	th(CKXH-DRV)	Hold time, DR valid after CLKX high	P – 10		8P	– 10		ns
M41	tsu(FXL-CKXH)	Setup time, FSX low before CLKX high			16P	+ 10		ns
M42	tc(CKX)	Cycle time, CLKX	2P			16P		ns

(1)Not production tested.

Table 6-57. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)(1) (2)

NO.		PARAMETER	MASTER		SLAVE		UNIT
			MIN	MAX	MIN	MAX
M34	th(CKXL-FXL)	Hold time, FSX low after CLKX low	P				ns
M35	td(FXL-CKXH)	Delay time, FSX low to CLKX high	2P				ns
M37	tdis(CKXL-DXHZ)	Disable time, DX high impedance following last data bit	P + 6		7P + 6		ns
		from CLKX low
M38	td(FXL-DXV)	Delay time, FSX low to DX valid	6		4P + 6		ns

(1)Not production tested.

(2)2P = 1/CLKG

For all SPI slave modes, CLKX has to be minimum eight CLKG cycles. Also, CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1. With maximum LSPCLK speed of 75 MHz, CLKX maximum frequency is LSPCLK/16 , that is 4.5 MHz and P = 13.3 ns.

LSB	M41	MSB
CLKX
M34	M35
FSX

M42

	M37	M38
DX	Bit 0	Bit(n-1)	(n-2)	(n-3)	(n-4)
		M39	M40
DR	Bit 0	Bit(n-1)	(n-2)	(n-3)	(n-4)

Figure 6-44. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0

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