Texas Instruments SM320F2812-HT specifications M58

SM320F2812-HT

SGUS062A –JUNE 2009 –REVISED APRIL 2010 www.ti.com

Table 6-60. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)(1)

NO.			MASTER		SLAVE		UNIT
			MIN MAX		MIN	MAX
M58	tsu(DRV-CKXL)	Setup time, DR valid before CLKX low	P – 10	8P	– 10		ns
M59	th(CKXL-DRV)	Hold time, DR valid after CLKX low	P – 10	8P	– 10		ns
M60	tsu(FXL-CKXL)	Setup time, FSX low before CLKX low		16P	+ 10		ns
M61	tc(CKX)	Cycle time, CLKX	2P		16P		ns

(1)Not production tested.

Table 6-61. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)(1) (2)

NO.		PARAMETER	MASTER (3)	SLAVE		UNIT
			MIN MAX	MIN	MAX
M53	th(CKXH-FXL)	Hold time, FSX low after CLKX high	P			ns
M54	td(FXL-CKXL)	Delay time, FSX low to CLKX low	2P			ns
M56	tdis(CKXH-DXHZ)	Disable time, DX high impedance following last data bit from CLKX	P + 6	7P + 6		ns
		high
M57	td(FXL-DXV)	Delay time, FSX low to DX valid	6	4P + 6		ns

(1)Not production tested.

(2)2P = 1/CLKG

For all SPI slave modes, CLKX has to be minimum eight CLKG cycles. Also, CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1. With maximum LSPCLK speed of 75 MHz, CLKX maximum frequency is LSPCLK/16, that is 4.5 MHz and P = 13.3 ns.

(3)C = CLKX low pulse width = P D = CLKX high pulse width = P

LSB	M60
CLKX

M53

FSX

MSB

M54

M61

	M56	M57
DX	Bit 0	Bit(n-1)
		M58
DR	Bit 0	Bit(n-1)

M55

(n-2) (n-3) (n-4)

M59

(n-2) (n-3) (n-4)

Figure 6-46. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1

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