Texas Instruments SM320F2812-HT specifications SPI Slave Mode Timing

SM320F2812-HT

SGUS062A –JUNE 2009 –REVISED APRIL 2010							www.ti.com
	6.20	SPI Slave Mode Timing					113
	6.21	External Interface (XINTF) Timing					117
	6.22	XINTF Signal Alignment to XCLKOUT					121
	6.23	External Interface Read Timing					122
	6.24	External Interface Write Timing					123
	6.25	External Interface Ready-on-Read Timing With One External Wait State					125
	6.26	External Interface Ready-on-Write Timing With One External Wait State					128
	6.27		and				131
		XHOLD			XHOLDA
	6.28						132
		XHOLD/XHOLDA Timing
	6.29	On-ChipAnalog-to-Digital Converter					134
		6.29.1 ADC Absolute Maximum Ratings					134
		6.29.2 ADC Electrical Characteristics Over Recommended Operating Conditions					135
		6.29.3 Current Consumption for Different ADC Configurations (at 25-MHz ADCCLK)					136
		6.29.4 ADC Power-Up Control Bit Timing					137
		6.29.5		Detailed Description			138
			6.29.5.1			Reference Voltage	138
			6.29.5.2			Analog Inputs	138
			6.29.5.3			Converter	138
			6.29.5.4			Conversion Modes	138
		6.29.6 Sequential Sampling Mode (Single Channel) (SMODE = 0)					138
		6.29.7 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1)					140
		6.29.8 Definitions of Specifications and Terminology					141
			6.29.8.1			Integral Nonlinearity	141
			6.29.8.2			Differential Nonlinearity	141
			6.29.8.3			Zero Offset	141
			6.29.8.4			Gain Error	141
				6.29.8.5 Signal-to-Noise Ratio + Distortion (SINAD)			141
				6.29.8.6 Effective Number of Bits (ENOB)			141
				6.29.8.7 Total Harmonic Distortion (THD)			141
				6.29.8.8 Spurious Free Dynamic Range (SFDR)			141
	6.30	Multichannel Buffered Serial Port (McBSP) Timing					142
		6.30.1 McBSP Transmit and Receive Timing					142
		6.30.2 McBSP as SPI Master or Slave Timing					145
	6.31	Flash Timing					149
		6.31.1		Recommended Operating Conditions			149
7	Mechanical Data						151

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