Texas Instruments SM320F2812-HT Device Clock Table, Clock Requirements and Characteristics

SM320F2812-HT

SGUS062A –JUNE 2009 –REVISED APRIL 2010 www.ti.com

6.12 Device Clock Table

This section provides the timing requirements and switching characteristics for the various clock options available on the F2812 DSP. Table 6-3lists the cycle times of various clocks.

Table 6-3. Clock Table and Nomenclature

On-chip oscillator clock

tc(OSC), Cycle time

MIN	NOM MAX	UNIT
28.6	50	ns

XCLKIN

Frequency

tc(CI), Cycle time

Frequency

20	35	MHz
6.67	250	ns
4	150	MHz

SYSCLKOUT

tc(SCO), Cycle time

6.67 500 ns

XCLKOUT

Frequency

tc(XCO), Cycle time

2	150	MHz
6.67	2000	ns

HSPCLK

Frequency

tc(HCO), Cycle time

0.5		150	MHz
6.67	13.3(1)		ns

LSPCLK

Frequency

tc(LCO), Cycle time

Frequency

	75	(1)	150	MHz
13.3	26.6	(1)		ns
	37.5	(1)	75	MHz

ADC clock

tc(ADCCLK), Cycle time(2)

40 ns

SPI clock

Frequency

tc(SPC), Cycle time

25	MHz
50	ns

McBSP

Frequency

tc(CKG), Cycle time

Frequency

20	MHz
50	ns
20	MHz

XTIMCLK

tc(XTIM), Cycle time

Frequency

6.67	ns
150	MHz

(1)This is the default reset value if SYSCLKOUT = 150 MHz.

(2)The maximum value for ADCCLK frequency is 25 MHz. For SYSCLKOUT values of 25 MHz or lower, ADCCLK has to be SYSCLKOUT/2 or lower. ADCCLK = SYSCLKOUT is not a valid mode for any value of SYSCLKOUT.

6.13 Clock Requirements and Characteristics

6.13.1 Input Clock Requirements

The clock provided at the XCLKIN pin generates the internal CPU clock cycle.

Table 6-4. Input Clock Frequency(1)

		PARAMETER		MIN TYP	MAX	UNIT
			Resonator(2)	20	35
f	Input clock frequency		Crystal(2)	20	35	MHz
x
			XCLKIN	4	150
fl	Limp mode clock frequency				2	MHz

(1)Not production tested.

(2)Not guaranteed for TA > 125°C.

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