![](/images/new-backgrounds/1187548/187548213x1.webp)
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SpaceWire Router |
| UserManual | |
Issue: | 3.4 | ||
User Manual | |||
Date: | 11th July 2008 | ||
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Table 9-3 GAR Table Register Description
Address Range:
Bits | Name | Reset | Description | Read/Write |
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0 | RESERVED | ‘0’ | Reserved bit – always set to zero. | R |
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10:1 | REQUEST | Undefined | The request bits determine which output ports | R/W |
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| after power | the logical address will arbitrate for. When bit |
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| on. | 1 is set then SpaceWire port 1 will be |
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| Unaltered | requested. When bit 2 is set then SpaceWire |
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| port 2 will be accessed and so on. |
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| by reset. |
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| By setting more than one bit group adaptive |
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| routing can be used, allowing the input packet |
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| to arbitrate for more than one output port. |
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| If a write is performed and bits 10:1 are set to |
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| zero then the INVALID_ADDR bit will be set |
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| and all other bits will be set to zero |
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| Note: The configuration port (port 0) is not |
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| accessible through logical addresses. |
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28:11 | NOT USED | - | - | - |
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29 | DEL_HEAD | Undefined | Delete header: when set the leading header | R/W |
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| after power | byte of the input packet will be removed |
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| on. | before it is transferred to the output port. |
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| Unaltered |
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| by reset. |
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30 | PRIORITY | Undefined | When a packet has a logical address with an | R/W |
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| after power | entry in the priority filed of this register set, the |
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| on. | packet will be granted access to a particular |
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| Unaltered | output port in preference to packets with |
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| priority bit set to zero. |
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| by reset. |
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31 | INVALID_ADDR | ‘1’ | When the Invalid Address bit is set it indicates | R/W |
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| that the corresponding logical address is |
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| invalid. In this case, any packets arriving at |
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| the router with an invalid address are spilt and |
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| an address error is reported in the port status |
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| register. |
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Preliminary | 107 |