General Purpose Register, Time-Code Enable Register | Atmel SpW-10X

	SpW-10X	Ref.:	UoD_SpW-10X_
	SpaceWire Router		UserManual
	SpaceWire Router	Issue:	3.4
	User Manual	Issue:	3.4
	User Manual	Date:	11th July 2008

9.5.7 General Purpose Register

The general purpose register address is 262 (0x0000 0106).

The general purpose register contains 32-bits and may be set by a configuration write command to a user defined value as required. It may also be read with a configuration read command. The general purpose register has no effect on the operation of the router.

The least-significant 8-bits of the general purpose register are available on the multiplexed status pins, see section 6.3.

9.5.8 Time-Code Enable Register

The time-code enable register address is 263 (0x0000 0107).

The time-code enable register enables the passing of time-codes out of individual ports on the router. Bits 1 to 8 of the time-code enable register are used to enable time-code distribution through SpaceWire ports 1 to 8 respectively. If one of these bits is set to 1 then the corresponding SpaceWire port is enabled for time-code distribution and will send out a time-code when one is received by the router. For example, if bit-1 in the enable register is set to 1, time-codes are passed to SpaceWire port 1, whereas if bit-1 is set to 0, time-codes are not passed to SpaceWire port 1.

Bit-9 of the time-code enable register controls time-code distribution to the external time-code interface in a similar manner. Note that there is only one external time-code interface although there are two External ports.

The fields of the time-code enable register are shown in Figure 9-9 and described in Table 9-14.

31	13	12	11,10	9	8	1	0

Reserved

Time-code enable

External time-code interface enable

Not used

Time-code flag mode

Not used

Figure 9-9 Time-Code Enable Register Fields

Preliminary

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Atmel SpW-10X user manual General Purpose Register, Time-Code Enable Register

Contents

Issue Date Th July UoDSpW-10XUserManual Date Issue Comments Author Ref. UoDSpW-10X11th July SpW-10X Contents Control Logic and Operational Modes 103 Global Spacewire Link Control 128 136138 143 150151 15.16 List of Figures 100 List of Tables Able 9-7 E Xternal P ORT C ONTROL/S Tatus F Ields TERMS, Acronyms and Abbreviations Introduction Applicable Documents Document Number Document Title DocumentsRef. UoDSpW-10X UserManual Date 11th July STAND-ALONE Router User Applications Embedded Router Node Interface Expanding the Number of Router Ports Issue Date 11th July Expanding the number of SpaceWire Ports SpW-10X Functional Overview External Ports Spacewire Ports Configuration Port Routing TableRouting Control Logic and Crossbar CONTROL/STATUS Registers TIME-CODE Processing PIN Locations Pin Signal Type Description VSSA2 GND PFOLVDS33Z EXTOUTDATA90 PO44F EXTOUTDATA108 PO44F EXTTIMEOUT6 PO44F Device Interface Global Signals TestEn Spacewire SignalsSpW-10X SpaceWire Signals TestIOEn DOUTPlus3 DOUTMinus1DOUTPlus2 DOUTMinus2 DINMinus2 11th July DINPlus1DINMinus1 DINPlus2 Lvds Receiver Fail-Safe Resistors SpaceWire Input Fail Safe Resistors SpW-10X External Port Data Signals UserManual Issue Date 11th JulyExternal Port Interface Signals PinNo Dir Description Type EXT9INDATA5 TIME-CODE Signals Time-Code Signals PinNo Dir Description TypeSelexttime and the EXTTIMEIN70 Exttickin the value on EXTTIMEIN70 is EXTTIMEIN70 inputExttickout is asserted Normal Operation Status Interface SignalsLink error indication Signals PinNo Dir Description Type Power on Configuration Configuration interface timing specification Reset Configuration Signals Maps to 11th July Reset Configuration Signals Dir DescriptionFeedbdiv at reset Maps to PORTXRATE20 Porstartonreqn Lvds Reference POWER, GROUND, PLL and Lvds SignalsGeneral Decoupling PLL with external components External Port Interface Operation Interface Operations TIME-CODE Interface Operation External port read timing specification Time-Code Output Interface Status Interface Operation Status Output Bits Reset configuration interface timing specification Reset Configuration Interface Operation Packet Addresses Spacewire Router Packet Types Packet Priority Packet Header DeletionPacket Priority Mapping Packet Address Physical Port type Invalid Addresses Command Packets Supported CommandsData Packets Read Command Read Single Address Command Format Issue Date Th July Read Single Address Characteristics SpW-10X EOP Read Incrementing Command Issue Date Th July Read Incrementing Address Characteristics Data Length MS 11th July 00h 11 Read-Modify-Write Command Characteristics Read Modify Write Command Preliminary66 RMW Read-Modify-Write example operation FEh 00h 14 Write Command Characteristics Write Command FEh 01h CRC MSB Command Error Response StatusCode SpW-10X Local Source Path Address Command Packet Cyclic Redundancy Check Source Path Address Field Date 11 th July Command Packet Fill Bytes Auto-Start Spacewire Link ControlDefault operating mode Control Logic and Operational Modes Automatic deactivate driver mode Link-Disable Deactivate driver operating mode Txrate +1 Setting the SpaceWire port transmit data rate TX 10MbitDIV +1 Setting SpaceWire Transmit Data Rate Global Spacewire Link Control Start on request mode Disable on Silence modeCfgstartonreq bit Packet address error Control Logic and RoutingArbitration Arbitration of packets with matching priority Arbitration of three packets with matching priority Arbitration of packets with different priority SpW-10X SpW-10X 10 Normal group adaptive routing Group Adaptive Routing Loop-back with Self-Addressing 11 Group adaptive routing when other ports busy 13 Packet Self-Addressing mode Blocked destination Packet Blocking 14 Destination Node Blocked a Blocking Allowed Mode 16 Destination Node Blocked c Watchdog timer mode Blocking Allowed 19 Destination Node Blocked Watchdog Mode c 21 Source Node Stalled a 100 101 102 Internal Memory MAP Register Definitions Register Addresses Summary Group Adaptive Routing Table Registers 11th July Configuration Register Addresses 106 Bits Name Reset Description Read/Write Value Issue Date Th July GAR Table Register Description Configuration Port Control/Status Register Fields Port CONTROL/STATUS RegistersGeneric port control/status register fields 11th July Bits Name Reset Description Read/Write Value Configuration port control/status register fields 110 111 SpaceWire Port Control/Status Register Fields SpaceWire port control/status register bits 113 114 External port control/status register bits Router CONTROL/STATUS RegistersNetwork Discovery Register Router Identity Register Router Control Register Fields Router Control Register 118 119 Error Active Register Fields Error active Register Time-Code Register Fields Time-Code Register Device Manufacturer and Chip ID Register General Purpose Register Time-Code Enable Register Transmit Clock Control Register 125 126 Writing to a READ-ONLY Register Destination Key RegisterUnused Registers and Register Bits Empty packets Switching Characteristics Clock and Reset Timing ParametersSerial Signals Timing Parameters External port input Fifo timing parameters External Port Timing Parameters TIME-CODE Interface Timing Parameters Time-code Timectrrst interface ERROR/STATUS Interface Timing Parameters 132 Router Latency Switching LatencyLatency and Jitter Clock Periods Time-code Latency Issue Date Th July SpaceWire port to SpaceWire portSpaceWire port to External port External port to SpaceWire port 10.6.6 200M bits/s Input and Output Bit Rate Example Time-code Jitter Electrical Characteristics DC CharacteristicsOperating Conditions Symbol Description Value Units Reliabilty Information Absolute Maximum Ratings Symbol Description Value UnitsAbsolute Maximum Ratings Reliability Information Application Guidelines Example Circuit Diagram 139 PCB Design and Layout Guidelines Status / Power On Configuration Interface External PortsTime-code Interface PLL Layout Recommendations 12.2.10 PLL Anomalies Anomalies and Warnings 144 Data Strobe Reset Waveform Reset Anomaly 146 Reset Anomaly Workarounds Data Strobe Disable Waveform Parity Error Anomaly Parity Error ActionParity Error Anomaly No error end of packet inserted after parity error Parity Error Workaround Technical Support Document Changes Issue 3.3 to IssueIssue 3.2 to Issue Issue 3.1 to Issue Issue 2.5 to Issue Issue 3.0 to Issue Issue 2.4 to Issue Issue 2.3 to IssueIssue 2.2 to Issue Issue 1.6 to Issue Issue 2.1 to IssueIssue 2.0 to Issue Issue 1.7 to Issue Issue 1.0 to Issue Issue 1.1 to Issue