Atmel SpW-10X user manual Interface Operations, External Port Interface Operation

SpW-10X	Ref.:	UoD_SpW-10X_
SpaceWire Router		UserManual
	Issue:	3.4
User Manual
	Date:	11th July 2008

6. INTERFACE OPERATIONS

This section describes the operation of the external FIFO port, time-code interface and status/power on configuration interface.

First a note on the terminology used: Signals are given a name (e.g. EXT_IN_FULL) and a logic level (e.g. _N). The term asserted is used when the signal state reflects the signal name e.g. EXT_IN_FULL is asserted when the external input FIFO is full. The term de-asserted is used when the signal state is the inverse of the signal name e.g. EXT_IN_FULL is de-asserted when the external input FIFO is not full. The logic level when a signal is asserted is indicated by the logic level extension to the signal name. If there is no extension then when the signal is asserted it is logic 1 (high). If the _N extension is present then when the signal is asserted it is logic 0 (low). For example, EXT_IN_FULL_N asserted means that the physical signal is logic 0 (low) when the external input FIFO is full.

6.1 EXTERNAL PORT INTERFACE OPERATION

In this section the external port interface operation is described.

1 2

CLK

EXT_IN_FULL_Nx

EXT_IN_DATAx

EXT_IN_WRITE_Nx

3 4

DATA

5 6

7 8 9 10 11 12

EOP DATA DATA

Figure 6-1 External port write timing specification

The operation of the External port during write operations starts with the EXT_IN_FULL_N signals being de-asserted (going high) by the router (at clock cycle 2 in Figure 6-1) to indicate to the external system that the router has room for more data and is ready to receive it through the External port. The External system then puts data onto the EXT_IN_DATA data lines and asserts EXT_IN_WRITE_N (goes low) to transfer data into the External port on the next rising edge of SYSCLK. As long as there is room for new data (EXT_IN_FULL_N is de-asserted (high) the writer access is performed as long as EXT_IN_WRITE_N is asserted (low). If no room is available the write access is ignored (cycle 9 and 10 in Figure 6-1) and will be performed when room has become available if EXT_IN_WRITE_N is still asserted (low). Therefore the data (EXT_IN_DATA) must be valid at that time.

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