Register Definitions, Internal Memory MAP | Atmel SpW-10X specs

	SpW-10X	Ref.:	UoD_SpW-10X_
	SpaceWire Router		UserManual
	SpaceWire Router	Issue:	3.4
	User Manual	Issue:	3.4
	User Manual	Date:	11th July 2008

9. REGISTER DEFINITIONS

This section describes the internal configuration registers of the SpW-10X Router.

The following subsections contain register bit description tables which hold the following information:

•The bit numbers of each field

•A descriptive name for each field

•The reset value for each field

•A description of what the each field in the register is used for

•An indication of whether the field is readable and/or writeable by a configuration command.

The internal register size is 32 bits unless otherwise specified in the register description. There are 263 registers in the configuration port addresses. Registers that are shorter than 32-bits or that have unused fields will return zero in all the unused bit positions when read. The unused bit positions are ignored during writing but should in any case be set to zero.

9.1 INTERNAL MEMORY MAP

The memory map for the SpaceWire Router is shown in Figure 9-1.

255

32

31

0

GROUP ADAPTIVE ROUTING TABLE REGISTERS

PORT

CONTROL/STATUS

REGISTERS

Address bit-8 = 0

255

0

ROUTER

CONTROL/STATUS

REGISTERS

Address bit-8 = 1

Figure 9-1 Router Internal Memory Map

The Group Adaptive Routing (GAR) registers map SpaceWire logical addresses 32-255 to the physical ports – SpaceWire ports or External ports. The link control/status registers are used to configure the ports and router functions and to report status information. The router control/status

Preliminary

103

Image 103

Atmel SpW-10X user manual Register Definitions, Internal Memory MAP

Contents

UoDSpW-10X Issue Date Th JulyUserManual Ref. UoDSpW-10X Date Issue Comments Author11th July SpW-10X Contents Control Logic and Operational Modes 103 Global Spacewire Link Control 136 128138 150 143151 15.16 List of Figures 100 List of Tables Able 9-7 E Xternal P ORT C ONTROL/S Tatus F Ields TERMS, Acronyms and Abbreviations Introduction Applicable Documents Document Number Document Title DocumentsRef. UoDSpW-10X UserManual Date 11th July STAND-ALONE Router User Applications Embedded Router Node Interface Expanding the Number of Router Ports Issue Date 11th July Expanding the number of SpaceWire Ports SpW-10X Functional Overview External Ports Spacewire Ports Routing Table Configuration PortRouting Control Logic and Crossbar CONTROL/STATUS Registers TIME-CODE Processing PIN Locations Pin Signal Type Description VSSA2 GND PFOLVDS33Z EXTOUTDATA90 PO44F EXTOUTDATA108 PO44F EXTTIMEOUT6 PO44F Device Interface Global Signals TestEn Spacewire SignalsSpW-10X SpaceWire Signals TestIOEn DOUTPlus3 DOUTMinus1DOUTPlus2 DOUTMinus2 DINMinus2 11th July DINPlus1DINMinus1 DINPlus2 Lvds Receiver Fail-Safe Resistors SpaceWire Input Fail Safe Resistors SpW-10X UserManual Issue Date 11th July External Port Data SignalsExternal Port Interface Signals PinNo Dir Description Type EXT9INDATA5 Time-Code Signals PinNo Dir Description Type TIME-CODE SignalsSelexttime and the EXTTIMEIN70 EXTTIMEIN70 input Exttickin the value on EXTTIMEIN70 isExttickout is asserted Normal Operation Status Interface SignalsLink error indication Signals PinNo Dir Description Type Power on Configuration Configuration interface timing specification Reset Configuration Signals Maps to 11th July Reset Configuration Signals Dir DescriptionFeedbdiv at reset Maps to PORTXRATE20 Porstartonreqn Lvds Reference POWER, GROUND, PLL and Lvds SignalsGeneral Decoupling PLL with external components External Port Interface Operation Interface Operations TIME-CODE Interface Operation External port read timing specification Time-Code Output Interface Status Interface Operation Status Output Bits Reset configuration interface timing specification Reset Configuration Interface Operation Packet Addresses Spacewire Router Packet Types Packet Header Deletion Packet PriorityPacket Priority Mapping Packet Address Physical Port type Invalid Addresses Supported Commands Command PacketsData Packets Read Command Read Single Address Command Format Issue Date Th July Read Single Address Characteristics SpW-10X EOP Read Incrementing Command Issue Date Th July Read Incrementing Address Characteristics Data Length MS 11th July 00h 11 Read-Modify-Write Command Characteristics Read Modify Write Command Preliminary66 RMW Read-Modify-Write example operation FEh 00h 14 Write Command Characteristics Write Command FEh 01h CRC MSB Status Command Error ResponseCode SpW-10X Local Source Path Address Command Packet Cyclic Redundancy Check Source Path Address Field Date 11 th July Command Packet Fill Bytes Auto-Start Spacewire Link ControlDefault operating mode Control Logic and Operational Modes Automatic deactivate driver mode Link-Disable Deactivate driver operating mode Txrate +1 Setting the SpaceWire port transmit data rate TX 10MbitDIV +1 Setting SpaceWire Transmit Data Rate Global Spacewire Link Control Disable on Silence mode Start on request modeCfgstartonreq bit Control Logic and Routing Packet address errorArbitration Arbitration of packets with matching priority Arbitration of three packets with matching priority Arbitration of packets with different priority SpW-10X SpW-10X 10 Normal group adaptive routing Group Adaptive Routing Loop-back with Self-Addressing 11 Group adaptive routing when other ports busy 13 Packet Self-Addressing mode Blocked destination Packet Blocking 14 Destination Node Blocked a Blocking Allowed Mode 16 Destination Node Blocked c Watchdog timer mode Blocking Allowed 19 Destination Node Blocked Watchdog Mode c 21 Source Node Stalled a 100 101 102 Internal Memory MAP Register Definitions Register Addresses Summary Group Adaptive Routing Table Registers 11th July Configuration Register Addresses 106 Bits Name Reset Description Read/Write Value Issue Date Th July GAR Table Register Description Port CONTROL/STATUS Registers Configuration Port Control/Status Register FieldsGeneric port control/status register fields 11th July Bits Name Reset Description Read/Write Value Configuration port control/status register fields 110 111 SpaceWire Port Control/Status Register Fields SpaceWire port control/status register bits 113 114 Router CONTROL/STATUS Registers External port control/status register bitsNetwork Discovery Register Router Identity Register Router Control Register Fields Router Control Register 118 119 Error Active Register Fields Error active Register Time-Code Register Fields Time-Code Register Device Manufacturer and Chip ID Register General Purpose Register Time-Code Enable Register Transmit Clock Control Register 125 126 Writing to a READ-ONLY Register Destination Key RegisterUnused Registers and Register Bits Empty packets Clock and Reset Timing Parameters Switching CharacteristicsSerial Signals Timing Parameters External port input Fifo timing parameters External Port Timing Parameters TIME-CODE Interface Timing Parameters Time-code Timectrrst interface ERROR/STATUS Interface Timing Parameters 132 Router Latency Switching LatencyLatency and Jitter Clock Periods Time-code Latency Issue Date Th July SpaceWire port to SpaceWire portSpaceWire port to External port External port to SpaceWire port 10.6.6 200M bits/s Input and Output Bit Rate Example Time-code Jitter DC Characteristics Electrical CharacteristicsOperating Conditions Symbol Description Value Units Reliabilty Information Absolute Maximum Ratings Symbol Description Value UnitsAbsolute Maximum Ratings Reliability Information Application Guidelines Example Circuit Diagram 139 PCB Design and Layout Guidelines External Ports Status / Power On Configuration InterfaceTime-code Interface PLL Layout Recommendations 12.2.10 PLL Anomalies Anomalies and Warnings 144 Data Strobe Reset Waveform Reset Anomaly 146 Reset Anomaly Workarounds Data Strobe Disable Waveform Parity Error Action Parity Error AnomalyParity Error Anomaly No error end of packet inserted after parity error Parity Error Workaround Technical Support Document Changes Issue 3.3 to IssueIssue 3.2 to Issue Issue 3.1 to Issue Issue 2.5 to Issue Issue 3.0 to Issue Issue 2.3 to Issue Issue 2.4 to IssueIssue 2.2 to Issue Issue 1.6 to Issue Issue 2.1 to IssueIssue 2.0 to Issue Issue 1.7 to Issue Issue 1.0 to Issue Issue 1.1 to Issue