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| Ref.: |
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| SpaceWire Router |
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| Issue: | 3.4 |
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| User Manual |
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| Date: | 11th July 2008 |
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| Table |
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Bits | Name | Reset Value |
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1:0 | TXDIV | “01” |
| Transmit clock internal PLL output |
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| divider. Selects the divided output from |
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| the transmit clock as follows |
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| “00” Æ divide by 2 |
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| “01” Æ divide by 4 |
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| “10” Æ divide by 8 |
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| “11” Æ divide by 8 |
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| Example: If the PLL output frequency is |
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| 200MHz (set by FEEDBDIV, see section |
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| 5.1) and TXDIV = 01 then the transmit |
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| clock frequency will be 50MHz and the |
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| transmit data rate will be 100Mbit/s |
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7:2 | Not used | All bits set to zero |
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15:8 | Enable clock | All bits set to 1 |
| Enable the transmit clock trees. Setting a | R/W |
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| bit to zero disables the transmit clock for |
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| the corresponding SpaceWire port, i.e. |
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| clearing bit 8 causes the transmit clock |
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| for SpaceWire port 1to be stopped. |
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20:16 | Tx10MbitDIV | Dependent on |
| Set the default 10Mbit/s data rate divider | R/W |
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| FEEDBDIV at reset |
| value. The Tx10MbitDIV value should be |
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| FEEDBDIV=“000” |
| set as described in section 8.1.6. |
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| Æ “00100” |
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| FEEDBDIV=“001” |
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| Æ “00101” |
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| FEEDBDIV=“010” |
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| Æ “00110” |
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| FEEDBDIV=“011” |
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| Æ “00111” |
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| FEEDBDIV=“100” |
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| Æ “01000” |
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| FEEDBDIV=“101” |
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| Æ “01001” |
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| FEEDBDIV=“110” |
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| Æ “01001” |
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| FEEDBDIV=“111” |
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| Æ “01001” |
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31:21 | Not used | All bits set to zero |
| - |
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| Preliminary |
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