
| Ref.: |
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SpaceWire Router |
| UserManual | |
Issue: | 3.4 | ||
User Manual | |||
Date: | 11th July 2008 | ||
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Table
PinNo | Signal | Dir | Description | Type |
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2 | CLK | In | System clock. Provides the reference clock for all | CMOS3V3 |
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| modules except the interface receivers. |
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3 | RST_N | In | Asynchronous system reset (active low). | CMOS3V3 |
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4 | TestIOEn | In | ASIC Test control signal; Shall be connected to | CMOS3V3; |
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| logic ‘0’ during normal operation. | Internal |
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| Tie to ground. |
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5 | TestEn | In | ASIC Test control signal; Shall be connected to | CMOS3V3; |
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| logic ‘0’ during normal operation. | Internal |
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| Tie to ground. |
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10 | FEEDBDIV(2) | In | Set the output clock rate of the internal PLL as | CMOS3V3; |
9 | FEEDBDIV(1) |
| follows: | Internal |
6 | FEEDBDIV(0) |
| “000” Æ 100MHz |
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| “001” Æ 120MHz |
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| “010” Æ 140MHz |
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| “011” Æ 160MHz |
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| “100” Æ 180MHz |
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| “101” Æ 200MHz |
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| “110” Æ 200MHz |
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| “111” Æ 200MHz |
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| See section 8.1.6 for setting the transmit rate. |
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See section 10.1 for timing details.
WARNING
Simultaneous data/strobe transitions can occur during reset and power up. This is not a problem when connected to SpaceWire compliant devices but is a problem when connected to
5.2 SPACEWIRE SIGNALS
5.2.1 SpW-10X SpaceWire Signals
The SpaceWire interface signals are listed in Table
Preliminary | 32 |