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| Ref.: |
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| SpaceWire Router |
| UserManual |
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| Issue: | 3.4 |
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| User Manual |
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| Date: | 11th July 2008 |
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146 | EXT10_IN_DATA(3) |
| (0)(dddddddd) - Data byte |
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145 | EXT10_IN_DATA(2) |
| (1)(XXXXXXX0) - EOP. |
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144 | EXT10_IN_DATA(1) |
| (1)(XXXXXXX1) - EEP. |
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143 | EXT10_IN_DATA(0) |
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| Bit 7 is the most significant bit of the data byte. |
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| connected to these inputs if External FIFO port |
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| 10 is not being used. |
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152 | EXT10_IN_FULL_N | Out | FIFO ready signal for external input port one. | CMOS3V3 |
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| When high there is space in the FIFO so it can |
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| be written to. When low the FIFO is full. |
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153 | EXT10_IN_WRITE_N | In | Asserted (low) to write to the external input | CMOS3V3 |
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| port one FIFO. |
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| A |
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| connected to this input if External FIFO port 10 |
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| is not being used. |
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See section 6.1 for information on the operation of the external ports and section 10.3 for timing details.
5.4 TIME-CODE SIGNALS
The
Figure
Table 5-4 Time-Code Signals
PinNo | Signal | Dir | Description | Type |
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158 | EXT_TICK_IN | In | The rising edge of the EXT_TICK_IN signal is used | CMOS3V3 |
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| to indicate when a |
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| rising edge of the EXT_TICK_IN signal the |
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| SEL_EXT_TIME signal is sampled to determine if |
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| the |
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| EXT_TIME_IN(7:0). |
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| The SEL_EXT_TIME and the EXT_TIME_IN(7:0) |
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| signals must be set up prior to the rising edge of |
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| EXT_TICK_IN and must be held static sometime |
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| afterwards. See section 10.4 for timing details. |
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| If the |
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| Preliminary | 39 |