Ref. UoDSpW-10X, 11th July, Date Issue Comments Author | Atmel

				SpW-10X	Ref.: UoD_SpW-10X_
			SpaceWire Router					UserManual
			SpaceWire Router		Issue:			3.4
				User Manual	Issue:			3.4
				User Manual	Date:			11th July 2008

Document Change log
	Date	Issue		Comments				Author
19th-March-2004		Issue 1.0		Initial draft version			Chris McClements
26th-August-2004		Issue 1.2		Timing for FPGA model added			Chris McClements
16 November 2004		Issue 1.3		Register Definitions Updated			Chris McClements

27 April 2004		Issue 1.4	Latency and Jitter Specifications				Chris McClements
				added

2 May 2005		Issue 1.5	Footer indicates “Preliminary.”				Steve Parkes
				Section 8.6 subject to change
				notice added to front page.

21 December 2005		Issue 1.6	RMAP section added				Chris McClements

19th July 2006		Issue 1.7	Corrections and clarifications				Chris McClements
18th August 2006		Issue 2.0	Editorial changes and				Steve Parkes
				clarifications

3rd July 2007		Issue 2.1	Added sections on ASIC pin				Chris McClements
				placement, ASIC power			Steve Parkes
				consumption, bias resistors,			Steve Parkes
				consumption, bias resistors,
				phase locked loop and
				anomalies.

28th September 2007		Issue 2.2	Modifications before handed to				Chris McClements,
				Atmel			Gerald Kempf

4th October 2007		Issue 2.3	Modifications to SpaceWire				Chris McClements,
				signal names (Map pin 1 to 0)			Gerald Kempf

3rd December 2007		Issue 2.4	Updates as user manual.				Chris McClements,
				Changed document name to			Gerald Kempf
				UoD_SpW_10X_UserManual.doc

11th December 2007		Issue 2.5	Redistribute with PLL settings				Chris McClements
							Gerald Kempf

18th January 2008		Issue 3.0	Major edit providing clarifications				Steve Parkes
				and additional application details
				throughout document.
				Section added on Application
				Guidelines giving example circuit
				diagram and PCB layout


				Preliminary				2

Image 2

Atmel user manual Ref. UoDSpW-10X, 11th July, Date Issue Comments Author

Contents

UserManual Issue Date Th JulyUoDSpW-10X 11th July Date Issue Comments AuthorRef. UoDSpW-10X SpW-10X Contents Control Logic and Operational Modes Global Spacewire Link Control 103 138 128136 151 143150 15.16 List of Figures 100 List of Tables Able 9-7 E Xternal P ORT C ONTROL/S Tatus F Ields Introduction TERMS, Acronyms and Abbreviations Date 11th July DocumentsRef. UoDSpW-10X UserManual Applicable Documents Document Number Document Title User Applications STAND-ALONE Router Node Interface Embedded Router Issue Date 11th July Expanding the Number of Router Ports Expanding the number of SpaceWire Ports SpW-10X Functional Overview Spacewire Ports External Ports Routing Control Logic and Crossbar Configuration PortRouting Table TIME-CODE Processing CONTROL/STATUS Registers Pin Signal Type Description PIN Locations VSSA2 GND PFOLVDS33Z EXTOUTDATA90 PO44F EXTOUTDATA108 PO44F EXTTIMEOUT6 PO44F Global Signals Device Interface TestIOEn Spacewire SignalsSpW-10X SpaceWire Signals TestEn DOUTMinus2 DOUTMinus1DOUTPlus2 DOUTPlus3 DINPlus2 11th July DINPlus1DINMinus1 DINMinus2 SpaceWire Input Fail Safe Resistors Lvds Receiver Fail-Safe Resistors SpW-10X External Port Interface Signals PinNo Dir Description Type External Port Data SignalsUserManual Issue Date 11th July EXT9INDATA5 Selexttime and the EXTTIMEIN70 TIME-CODE SignalsTime-Code Signals PinNo Dir Description Type Exttickout is asserted Exttickin the value on EXTTIMEIN70 isEXTTIMEIN70 input Power on Configuration Status Interface SignalsLink error indication Signals PinNo Dir Description Type Normal Operation Reset Configuration Signals Configuration interface timing specification Maps to PORTXRATE20 11th July Reset Configuration Signals Dir DescriptionFeedbdiv at reset Maps to Porstartonreqn Decoupling POWER, GROUND, PLL and Lvds SignalsGeneral Lvds Reference PLL with external components Interface Operations External Port Interface Operation External port read timing specification TIME-CODE Interface Operation Status Interface Operation Time-Code Output Interface Status Output Bits Reset Configuration Interface Operation Reset configuration interface timing specification Spacewire Router Packet Types Packet Addresses Packet Priority Mapping Packet Address Physical Port type Packet PriorityPacket Header Deletion Invalid Addresses Data Packets Command PacketsSupported Commands Read Command Issue Date Th July Read Single Address Characteristics Read Single Address Command Format SpW-10X EOP Read Incrementing Command Issue Date Th July Read Incrementing Address Characteristics Data Length MS 11th July 00h Read Modify Write Command 11 Read-Modify-Write Command Characteristics Preliminary66 RMW Read-Modify-Write example operation FEh 00h Write Command 14 Write Command Characteristics FEh 01h CRC MSB Code Command Error ResponseStatus SpW-10X Command Packet Cyclic Redundancy Check Local Source Path Address Source Path Address Field Command Packet Fill Bytes Date 11 th July Control Logic and Operational Modes Spacewire Link ControlDefault operating mode Auto-Start Link-Disable Automatic deactivate driver mode Deactivate driver operating mode Setting the SpaceWire port transmit data rate Txrate +1 Setting SpaceWire Transmit Data Rate TX 10MbitDIV +1 Global Spacewire Link Control Cfgstartonreq bit Start on request modeDisable on Silence mode Arbitration Packet address errorControl Logic and Routing Arbitration of packets with matching priority Arbitration of three packets with matching priority Arbitration of packets with different priority SpW-10X SpW-10X Group Adaptive Routing 10 Normal group adaptive routing 11 Group adaptive routing when other ports busy Loop-back with Self-Addressing 13 Packet Self-Addressing mode Packet Blocking Blocked destination Blocking Allowed Mode 14 Destination Node Blocked a 16 Destination Node Blocked c Watchdog timer mode 19 Destination Node Blocked Watchdog Mode c Blocking Allowed 21 Source Node Stalled a 100 101 102 Register Definitions Internal Memory MAP Register Addresses Summary 11th July Configuration Register Addresses Group Adaptive Routing Table Registers 106 Issue Date Th July GAR Table Register Description Bits Name Reset Description Read/Write Value Generic port control/status register fields Configuration Port Control/Status Register FieldsPort CONTROL/STATUS Registers Configuration port control/status register fields 11th July Bits Name Reset Description Read/Write Value 110 111 SpaceWire port control/status register bits SpaceWire Port Control/Status Register Fields 113 114 Network Discovery Register External port control/status register bitsRouter CONTROL/STATUS Registers Router Identity Register Router Control Register Router Control Register Fields 118 119 Error active Register Error Active Register Fields Time-Code Register Time-Code Register Fields Device Manufacturer and Chip ID Register Time-Code Enable Register General Purpose Register Transmit Clock Control Register 125 126 Empty packets Destination Key RegisterUnused Registers and Register Bits Writing to a READ-ONLY Register Serial Signals Timing Parameters Switching CharacteristicsClock and Reset Timing Parameters External Port Timing Parameters External port input Fifo timing parameters TIME-CODE Interface Timing Parameters ERROR/STATUS Interface Timing Parameters Time-code Timectrrst interface 132 Clock Periods Switching LatencyLatency and Jitter Router Latency External port to SpaceWire port Issue Date Th July SpaceWire port to SpaceWire portSpaceWire port to External port Time-code Latency Time-code Jitter 10.6.6 200M bits/s Input and Output Bit Rate Example Operating Conditions Symbol Description Value Units Electrical CharacteristicsDC Characteristics Reliability Information Absolute Maximum Ratings Symbol Description Value UnitsAbsolute Maximum Ratings Reliabilty Information Example Circuit Diagram Application Guidelines 139 PCB Design and Layout Guidelines Time-code Interface Status / Power On Configuration InterfaceExternal Ports 12.2.10 PLL PLL Layout Recommendations Anomalies and Warnings Anomalies 144 Reset Anomaly Data Strobe Reset Waveform 146 Data Strobe Disable Waveform Reset Anomaly Workarounds Parity Error Anomaly Parity Error AnomalyParity Error Action Parity Error Workaround No error end of packet inserted after parity error Technical Support Issue 3.1 to Issue Issue 3.3 to IssueIssue 3.2 to Issue Document Changes Issue 3.0 to Issue Issue 2.5 to Issue Issue 2.2 to Issue Issue 2.4 to IssueIssue 2.3 to Issue Issue 1.7 to Issue Issue 2.1 to IssueIssue 2.0 to Issue Issue 1.6 to Issue Issue 1.1 to Issue Issue 1.0 to Issue