12.2.10 PLL, PLL Layout Recommendations | Atmel SpW-10X specification

	SpW-10X	Ref.:	UoD_SpW-10X_
	SpaceWire Router		UserManual
	SpaceWire Router	Issue:	3.4
	User Manual	Issue:	3.4
	User Manual	Date:	11th July 2008

12.2.10 PLL

See Figure 12-1 the internal wiring of PLL block to better understand the external board recommended layout. The Voltage drop between PLL loop filter (LF) and the PVCOBIAS pads will be converted into a current (Ivco) which will determine the VCO frequency. It is critical to avoid any disturbance of that voltage drop at this will translate directly to jitter in the VCO frequency.

Figure 12-1 PLL Layout Recommendations

The following layout recommendations apply to the PLL circuitry.

1.To minimize voltage parasitic through ground the loop filter and VCO bias components will have a separate ground plane underneath all PLL pins and components.

2.This PLL ground plane shall be connected at one point to the PLLVSS pad.

3.To minimize other electromagnetic crosstalk effects, SMD components should be used and placed as close as possible to the corresponding pads.

4.The PLL has been designed to exhibit low sensitivity to power supply variation. VDDPLL can be externally connected to the core array power supply but the cleaner that power supply the better the PLL performances is in terms of jitter. Separate 100 nF and 1 µF decoupling capacitors shall be provided for VDDPLL.

Preliminary

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Atmel SpW-10X user manual 12.2.10 PLL, PLL Layout Recommendations

Contents

UoDSpW-10X Issue Date Th JulyUserManual Ref. UoDSpW-10X Date Issue Comments Author11th July SpW-10X Contents Control Logic and Operational Modes Global Spacewire Link Control 103 136 128138 150 143151 15.16 List of Figures 100 List of Tables Able 9-7 E Xternal P ORT C ONTROL/S Tatus F Ields Introduction TERMS, Acronyms and Abbreviations Date 11th July DocumentsRef. UoDSpW-10X UserManual Applicable Documents Document Number Document Title User Applications STAND-ALONE Router Node Interface Embedded Router Issue Date 11th July Expanding the Number of Router Ports Expanding the number of SpaceWire Ports SpW-10X Functional Overview Spacewire Ports External Ports Routing Table Configuration PortRouting Control Logic and Crossbar TIME-CODE Processing CONTROL/STATUS Registers Pin Signal Type Description PIN Locations VSSA2 GND PFOLVDS33Z EXTOUTDATA90 PO44F EXTOUTDATA108 PO44F EXTTIMEOUT6 PO44F Global Signals Device Interface TestIOEn Spacewire SignalsSpW-10X SpaceWire Signals TestEn DOUTMinus2 DOUTMinus1DOUTPlus2 DOUTPlus3 DINPlus2 11th July DINPlus1DINMinus1 DINMinus2 SpaceWire Input Fail Safe Resistors Lvds Receiver Fail-Safe Resistors SpW-10X UserManual Issue Date 11th July External Port Data SignalsExternal Port Interface Signals PinNo Dir Description Type EXT9INDATA5 Time-Code Signals PinNo Dir Description Type TIME-CODE SignalsSelexttime and the EXTTIMEIN70 EXTTIMEIN70 input Exttickin the value on EXTTIMEIN70 isExttickout is asserted Power on Configuration Status Interface SignalsLink error indication Signals PinNo Dir Description Type Normal Operation Reset Configuration Signals Configuration interface timing specification Maps to PORTXRATE20 11th July Reset Configuration Signals Dir DescriptionFeedbdiv at reset Maps to Porstartonreqn Decoupling POWER, GROUND, PLL and Lvds SignalsGeneral Lvds Reference PLL with external components Interface Operations External Port Interface Operation External port read timing specification TIME-CODE Interface Operation Status Interface Operation Time-Code Output Interface Status Output Bits Reset Configuration Interface Operation Reset configuration interface timing specification Spacewire Router Packet Types Packet Addresses Packet Header Deletion Packet PriorityPacket Priority Mapping Packet Address Physical Port type Invalid Addresses Supported Commands Command PacketsData Packets Read Command Issue Date Th July Read Single Address Characteristics Read Single Address Command Format SpW-10X EOP Read Incrementing Command Issue Date Th July Read Incrementing Address Characteristics Data Length MS 11th July 00h Read Modify Write Command 11 Read-Modify-Write Command Characteristics Preliminary66 RMW Read-Modify-Write example operation FEh 00h Write Command 14 Write Command Characteristics FEh 01h CRC MSB Status Command Error ResponseCode SpW-10X Command Packet Cyclic Redundancy Check Local Source Path Address Source Path Address Field Command Packet Fill Bytes Date 11 th July Control Logic and Operational Modes Spacewire Link ControlDefault operating mode Auto-Start Link-Disable Automatic deactivate driver mode Deactivate driver operating mode Setting the SpaceWire port transmit data rate Txrate +1 Setting SpaceWire Transmit Data Rate TX 10MbitDIV +1 Global Spacewire Link Control Disable on Silence mode Start on request modeCfgstartonreq bit Control Logic and Routing Packet address errorArbitration Arbitration of packets with matching priority Arbitration of three packets with matching priority Arbitration of packets with different priority SpW-10X SpW-10X Group Adaptive Routing 10 Normal group adaptive routing 11 Group adaptive routing when other ports busy Loop-back with Self-Addressing 13 Packet Self-Addressing mode Packet Blocking Blocked destination Blocking Allowed Mode 14 Destination Node Blocked a 16 Destination Node Blocked c Watchdog timer mode 19 Destination Node Blocked Watchdog Mode c Blocking Allowed 21 Source Node Stalled a 100 101 102 Register Definitions Internal Memory MAP Register Addresses Summary 11th July Configuration Register Addresses Group Adaptive Routing Table Registers 106 Issue Date Th July GAR Table Register Description Bits Name Reset Description Read/Write Value Port CONTROL/STATUS Registers Configuration Port Control/Status Register FieldsGeneric port control/status register fields Configuration port control/status register fields 11th July Bits Name Reset Description Read/Write Value 110 111 SpaceWire port control/status register bits SpaceWire Port Control/Status Register Fields 113 114 Router CONTROL/STATUS Registers External port control/status register bitsNetwork Discovery Register Router Identity Register Router Control Register Router Control Register Fields 118 119 Error active Register Error Active Register Fields Time-Code Register Time-Code Register Fields Device Manufacturer and Chip ID Register Time-Code Enable Register General Purpose Register Transmit Clock Control Register 125 126 Empty packets Destination Key RegisterUnused Registers and Register Bits Writing to a READ-ONLY Register Clock and Reset Timing Parameters Switching CharacteristicsSerial Signals Timing Parameters External Port Timing Parameters External port input Fifo timing parameters TIME-CODE Interface Timing Parameters ERROR/STATUS Interface Timing Parameters Time-code Timectrrst interface 132 Clock Periods Switching LatencyLatency and Jitter Router Latency External port to SpaceWire port Issue Date Th July SpaceWire port to SpaceWire portSpaceWire port to External port Time-code Latency Time-code Jitter 10.6.6 200M bits/s Input and Output Bit Rate Example DC Characteristics Electrical CharacteristicsOperating Conditions Symbol Description Value Units Reliability Information Absolute Maximum Ratings Symbol Description Value UnitsAbsolute Maximum Ratings Reliabilty Information Example Circuit Diagram Application Guidelines 139 PCB Design and Layout Guidelines External Ports Status / Power On Configuration InterfaceTime-code Interface 12.2.10 PLL PLL Layout Recommendations Anomalies and Warnings Anomalies 144 Reset Anomaly Data Strobe Reset Waveform 146 Data Strobe Disable Waveform Reset Anomaly Workarounds Parity Error Action Parity Error AnomalyParity Error Anomaly Parity Error Workaround No error end of packet inserted after parity error Technical Support Issue 3.1 to Issue Issue 3.3 to IssueIssue 3.2 to Issue Document Changes Issue 3.0 to Issue Issue 2.5 to Issue Issue 2.3 to Issue Issue 2.4 to IssueIssue 2.2 to Issue Issue 1.7 to Issue Issue 2.1 to IssueIssue 2.0 to Issue Issue 1.6 to Issue Issue 1.1 to Issue Issue 1.0 to Issue