Atmel SpW-10X user manual Spacewire Ports, External Ports

		SpW-10X		Ref.:	UoD_SpW-10X_
		SpaceWire Router			UserManual
				Issue:	3.4
		User Manual
				Date:	11th July 2008
		Control		Routing
		L ogic
	SpaceWire			Table
	Port 1
	SpaceWire		Status/E rror
	Port 2
	SpaceWire		Registers
	Port 3				Status
	SpaceWire
					Outputs
Spa ce Wire	Port 4
	SpaceWire			Control
Interfaces	Port 5		Registers
	SpaceWire
	Port 6	Crossbar
	SpaceWire
		Sw itch
	Port 7		Configuration
	SpaceWire			Port
	Port 8
External	Input F IFO
Input/Outp ut	Output FIFO
	E xternal Port
External	Input F IFO		Time-Code		Time -Code
Input/Outp ut	Output FIFO
					Inputs /
	E xternal Port		Interface
					Outputs

Figure 3-1 SpaceWire router block diagram

The following paragraphs define the SpaceWire router functional logic blocks in more detail.

3.1 SPACEWIRE PORTS

The SpaceWire router has eight bi-directional SpaceWire links each conformant with the SpaceWire standard. Each SpaceWire link is controlled by an associated link register and routing control logic. Network level error recovery is performed when an error is detected on the SpaceWire link as defined in the SpaceWire standard. Packets received on SpaceWire links are routed by the routing control logic to the configuration port, other SpaceWire link ports or the external FIFO ports. Packets with invalid addresses are discarded by the SpaceWire router dependent on the packet address. The SpaceWire link status is recorded in the associated link register and error status is held by the router until cleared by a configuration command.

3.2 EXTERNAL PORTS

The SpaceWire router has two bi-directional parallel FIFO interfaces that can be used to connect the router to an external host system. The external port FIFO is two data characters deep. Each FIFO is

Preliminary 22