100 | Atmel SpW-10X instruction

SpW-10X	Ref.:	UoD_SpW-10X_
		UserManual
SpaceWire Router
	Issue:	3.4
User Manual	Date:	11th July 2008
FIGURE 8-8 ARBITRATION OF TWO PACKETS WITH DIFFERENT PRIORITY (1)		89
FIGURE 8-9 ARBITRATION OF TWO PACKETS WITH DIFFERENT PRIORITY (2)		91
FIGURE 8-10 NORMAL GROUP ADAPTIVE ROUTING		92
FIGURE 8-11 GROUP ADAPTIVE ROUTING WHEN OTHER PORTS BUSY		93
FIGURE 8-12 GROUP ADAPTIVE ROUTING WHEN PORTS NOT READY		93
FIGURE 8-13 PACKET SELF-ADDRESSING MODE		94
FIGURE 8-14 DESTINATION NODE BLOCKED (A)		96
FIGURE 8-15 DESTINATION NODE BLOCKED (B)		96
FIGURE 8-16 DESTINATION NODE BLOCKED (C)		97
FIGURE 8-17 DESTINATION NODE BLOCKED: WATCHDOG MODE (A)		97
FIGURE 8-18 DESTINATION NODE BLOCKED: WATCHDOG MODE (B)		97
FIGURE 8-19 DESTINATION NODE BLOCKED: WATCHDOG MODE (C)		98
FIGURE 8-20 DESTINATION NODE BLOCKED: WATCHDOG MODE (D)		98
FIGURE 8-21 SOURCE NODE STALLED (A)		99
FIGURE 8-22 SOURCE NODE STALLED (B)		99
FIGURE 8-23 SOURCE NODE STALLED (C)		99
FIGURE 8-24 SOURCE NODE STALLED (D)		99
FIGURE 8-25 SOURCE NODE STALLED: WATCHDOG MODE (A)		100
FIGURE 8-26 SOURCE NODE STALLED: WATCHDOG MODE (B)		100
FIGURE 8-27 SOURCE NODE STALLED: WATCHDOG MODE (C)		100
FIGURE 8-28 SOURCE NODE STALLED: WATCHDOG MODE (D)		100
FIGURE 9-1 ROUTER INTERNAL MEMORY MAP		103
FIGURE 9-2 GAR REGISTER FIELDS		105
FIGURE 9-3 SPACEWIRE PORT CONTROL/STATUS REGISTER FIELDS		112
FIGURE 9-4 NETWORK DISCOVERY REGISTER FIELDS		116
FIGURE 9-5 ROUTER CONTROL REGISTER FIELDS		117
FIGURE 9-6 ERROR ACTIVE REGISTER FIELDS		120
FIGURE 9-7 TIME-CODEREGISTER FIELDS		121
FIGURE 9-8 DEVICE MANUFACTURER AND CHIP ID REGISTER FIELDS		122
FIGURE 9-9 TIME-CODEENABLE REGISTER FIELDS		123
FIGURE 9-10 TRANSMIT CLOCK CONTROL REGISTER		125
FIGURE 10-1 DS MINIMUM CONSECUTIVE EDGE SEPARATION		128
FIGURE 10-2 EXTERNAL PORT INPUT FIFO TIMING PARAMETERS		129
FIGURE 10-3 EXTERNAL PORT OUTPUT FIFO TIMING PARAMETERS		129
FIGURE 10-4 TIME-CODEINPUT INTERFACE		130
FIGURE 10-5 TIME-CODEOUTPUT INTERFACE		131
FIGURE 10-6 TIME-CODETIME_CTR_RST INTERFACE		131
FIGURE 12-1 PLL LAYOUT RECOMMENDATIONS		142
FIGURE 13-1 RESET WAVEFORM		146
FIGURE 13-2 RESET WAVEFORM WITH DATA AND STROBE BOTH HIGH		146
FIGURE 13-3 GLITCHES ON DATA OR STROBE DURING RESET		146
FIGURE 13-4 SIMULTANEOUS TRANSITION OF DATA AND STROBE DURING RESET		146
Preliminary		11

Image 11

Atmel SpW-10X user manual 100

Contents

UserManual Issue Date Th JulyUoDSpW-10X 11th July Date Issue Comments AuthorRef. UoDSpW-10X SpW-10X Contents Control Logic and Operational Modes 103 Global Spacewire Link Control 138 128136 151 143150 15.16 List of Figures 100 List of Tables Able 9-7 E Xternal P ORT C ONTROL/S Tatus F Ields TERMS, Acronyms and Abbreviations Introduction Applicable Documents Document Number Document Title DocumentsRef. UoDSpW-10X UserManual Date 11th July STAND-ALONE Router User Applications Embedded Router Node Interface Expanding the Number of Router Ports Issue Date 11th July Expanding the number of SpaceWire Ports SpW-10X Functional Overview External Ports Spacewire Ports Routing Control Logic and Crossbar Configuration PortRouting Table CONTROL/STATUS Registers TIME-CODE Processing PIN Locations Pin Signal Type Description VSSA2 GND PFOLVDS33Z EXTOUTDATA90 PO44F EXTOUTDATA108 PO44F EXTTIMEOUT6 PO44F Device Interface Global Signals TestEn Spacewire SignalsSpW-10X SpaceWire Signals TestIOEn DOUTPlus3 DOUTMinus1DOUTPlus2 DOUTMinus2 DINMinus2 11th July DINPlus1DINMinus1 DINPlus2 Lvds Receiver Fail-Safe Resistors SpaceWire Input Fail Safe Resistors SpW-10X External Port Interface Signals PinNo Dir Description Type External Port Data SignalsUserManual Issue Date 11th July EXT9INDATA5 Selexttime and the EXTTIMEIN70 TIME-CODE SignalsTime-Code Signals PinNo Dir Description Type Exttickout is asserted Exttickin the value on EXTTIMEIN70 isEXTTIMEIN70 input Normal Operation Status Interface SignalsLink error indication Signals PinNo Dir Description Type Power on Configuration Configuration interface timing specification Reset Configuration Signals Maps to 11th July Reset Configuration Signals Dir DescriptionFeedbdiv at reset Maps to PORTXRATE20 Porstartonreqn Lvds Reference POWER, GROUND, PLL and Lvds SignalsGeneral Decoupling PLL with external components External Port Interface Operation Interface Operations TIME-CODE Interface Operation External port read timing specification Time-Code Output Interface Status Interface Operation Status Output Bits Reset configuration interface timing specification Reset Configuration Interface Operation Packet Addresses Spacewire Router Packet Types Packet Priority Mapping Packet Address Physical Port type Packet PriorityPacket Header Deletion Invalid Addresses Data Packets Command PacketsSupported Commands Read Command Read Single Address Command Format Issue Date Th July Read Single Address Characteristics SpW-10X EOP Read Incrementing Command Issue Date Th July Read Incrementing Address Characteristics Data Length MS 11th July 00h 11 Read-Modify-Write Command Characteristics Read Modify Write Command Preliminary66 RMW Read-Modify-Write example operation FEh 00h 14 Write Command Characteristics Write Command FEh 01h CRC MSB Code Command Error ResponseStatus SpW-10X Local Source Path Address Command Packet Cyclic Redundancy Check Source Path Address Field Date 11 th July Command Packet Fill Bytes Auto-Start Spacewire Link ControlDefault operating mode Control Logic and Operational Modes Automatic deactivate driver mode Link-Disable Deactivate driver operating mode Txrate +1 Setting the SpaceWire port transmit data rate TX 10MbitDIV +1 Setting SpaceWire Transmit Data Rate Global Spacewire Link Control Cfgstartonreq bit Start on request modeDisable on Silence mode Arbitration Packet address errorControl Logic and Routing Arbitration of packets with matching priority Arbitration of three packets with matching priority Arbitration of packets with different priority SpW-10X SpW-10X 10 Normal group adaptive routing Group Adaptive Routing Loop-back with Self-Addressing 11 Group adaptive routing when other ports busy 13 Packet Self-Addressing mode Blocked destination Packet Blocking 14 Destination Node Blocked a Blocking Allowed Mode 16 Destination Node Blocked c Watchdog timer mode Blocking Allowed 19 Destination Node Blocked Watchdog Mode c 21 Source Node Stalled a 100 101 102 Internal Memory MAP Register Definitions Register Addresses Summary Group Adaptive Routing Table Registers 11th July Configuration Register Addresses 106 Bits Name Reset Description Read/Write Value Issue Date Th July GAR Table Register Description Generic port control/status register fields Configuration Port Control/Status Register FieldsPort CONTROL/STATUS Registers 11th July Bits Name Reset Description Read/Write Value Configuration port control/status register fields 110 111 SpaceWire Port Control/Status Register Fields SpaceWire port control/status register bits 113 114 Network Discovery Register External port control/status register bitsRouter CONTROL/STATUS Registers Router Identity Register Router Control Register Fields Router Control Register 118 119 Error Active Register Fields Error active Register Time-Code Register Fields Time-Code Register Device Manufacturer and Chip ID Register General Purpose Register Time-Code Enable Register Transmit Clock Control Register 125 126 Writing to a READ-ONLY Register Destination Key RegisterUnused Registers and Register Bits Empty packets Serial Signals Timing Parameters Switching CharacteristicsClock and Reset Timing Parameters External port input Fifo timing parameters External Port Timing Parameters TIME-CODE Interface Timing Parameters Time-code Timectrrst interface ERROR/STATUS Interface Timing Parameters 132 Router Latency Switching LatencyLatency and Jitter Clock Periods Time-code Latency Issue Date Th July SpaceWire port to SpaceWire portSpaceWire port to External port External port to SpaceWire port 10.6.6 200M bits/s Input and Output Bit Rate Example Time-code Jitter Operating Conditions Symbol Description Value Units Electrical CharacteristicsDC Characteristics Reliabilty Information Absolute Maximum Ratings Symbol Description Value UnitsAbsolute Maximum Ratings Reliability Information Application Guidelines Example Circuit Diagram 139 PCB Design and Layout Guidelines Time-code Interface Status / Power On Configuration InterfaceExternal Ports PLL Layout Recommendations 12.2.10 PLL Anomalies Anomalies and Warnings 144 Data Strobe Reset Waveform Reset Anomaly 146 Reset Anomaly Workarounds Data Strobe Disable Waveform Parity Error Anomaly Parity Error AnomalyParity Error Action No error end of packet inserted after parity error Parity Error Workaround Technical Support Document Changes Issue 3.3 to IssueIssue 3.2 to Issue Issue 3.1 to Issue Issue 2.5 to Issue Issue 3.0 to Issue Issue 2.2 to Issue Issue 2.4 to IssueIssue 2.3 to Issue Issue 1.6 to Issue Issue 2.1 to IssueIssue 2.0 to Issue Issue 1.7 to Issue Issue 1.0 to Issue Issue 1.1 to Issue