SpW-10X | Ref.: | UoD_SpW-10X_ |
| | UserManual |
SpaceWire Router | | |
| Issue: | 3.4 |
User Manual | Date: | 11th July 2008 |
FIGURE 8-8 ARBITRATION OF TWO PACKETS WITH DIFFERENT PRIORITY (1) | 89 |
FIGURE 8-9 ARBITRATION OF TWO PACKETS WITH DIFFERENT PRIORITY (2) | 91 |
FIGURE 8-10 NORMAL GROUP ADAPTIVE ROUTING | 92 |
FIGURE 8-11 GROUP ADAPTIVE ROUTING WHEN OTHER PORTS BUSY | 93 |
FIGURE 8-12 GROUP ADAPTIVE ROUTING WHEN PORTS NOT READY | 93 |
FIGURE 8-13 PACKET SELF-ADDRESSING MODE | 94 |
FIGURE 8-14 DESTINATION NODE BLOCKED (A) | 96 |
FIGURE 8-15 DESTINATION NODE BLOCKED (B) | 96 |
FIGURE 8-16 DESTINATION NODE BLOCKED (C) | 97 |
FIGURE 8-17 DESTINATION NODE BLOCKED: WATCHDOG MODE (A) | 97 |
FIGURE 8-18 DESTINATION NODE BLOCKED: WATCHDOG MODE (B) | 97 |
FIGURE 8-19 DESTINATION NODE BLOCKED: WATCHDOG MODE (C) | 98 |
FIGURE 8-20 DESTINATION NODE BLOCKED: WATCHDOG MODE (D) | 98 |
FIGURE 8-21 SOURCE NODE STALLED (A) | 99 |
FIGURE 8-22 SOURCE NODE STALLED (B) | 99 |
FIGURE 8-23 SOURCE NODE STALLED (C) | 99 |
FIGURE 8-24 SOURCE NODE STALLED (D) | 99 |
FIGURE 8-25 SOURCE NODE STALLED: WATCHDOG MODE (A) | 100 |
FIGURE 8-26 SOURCE NODE STALLED: WATCHDOG MODE (B) | 100 |
FIGURE 8-27 SOURCE NODE STALLED: WATCHDOG MODE (C) | 100 |
FIGURE 8-28 SOURCE NODE STALLED: WATCHDOG MODE (D) | 100 |
FIGURE 9-1 ROUTER INTERNAL MEMORY MAP | 103 |
FIGURE 9-2 GAR REGISTER FIELDS | 105 |
FIGURE 9-3 SPACEWIRE PORT CONTROL/STATUS REGISTER FIELDS | 112 |
FIGURE 9-4 NETWORK DISCOVERY REGISTER FIELDS | 116 |
FIGURE 9-5 ROUTER CONTROL REGISTER FIELDS | 117 |
FIGURE 9-6 ERROR ACTIVE REGISTER FIELDS | 120 |
FIGURE 9-7 TIME-CODEREGISTER FIELDS | 121 |
FIGURE 9-8 DEVICE MANUFACTURER AND CHIP ID REGISTER FIELDS | 122 |
FIGURE 9-9 TIME-CODEENABLE REGISTER FIELDS | 123 |
FIGURE 9-10 TRANSMIT CLOCK CONTROL REGISTER | 125 |
FIGURE 10-1 DS MINIMUM CONSECUTIVE EDGE SEPARATION | 128 |
FIGURE 10-2 EXTERNAL PORT INPUT FIFO TIMING PARAMETERS | 129 |
FIGURE 10-3 EXTERNAL PORT OUTPUT FIFO TIMING PARAMETERS | 129 |
FIGURE 10-4 TIME-CODEINPUT INTERFACE | 130 |
FIGURE 10-5 TIME-CODEOUTPUT INTERFACE | 131 |
FIGURE 10-6 TIME-CODETIME_CTR_RST INTERFACE | 131 |
FIGURE 12-1 PLL LAYOUT RECOMMENDATIONS | 142 |
FIGURE 13-1 RESET WAVEFORM | 146 |
FIGURE 13-2 RESET WAVEFORM WITH DATA AND STROBE BOTH HIGH | 146 |
FIGURE 13-3 GLITCHES ON DATA OR STROBE DURING RESET | 146 |
FIGURE 13-4 SIMULTANEOUS TRANSITION OF DATA AND STROBE DURING RESET | 146 |
Preliminary | | 11 |
