Figure 13. Memory socket locations
Memory channels are organized as follows:
Processor 1 | channel 0: slots A1, A5 |
| channel 1: slots A2, A6 |
| channel 2: slots A3, A7 |
| channel 3: slots A4, A8 |
Processor 2 | channel 0: slots B1, B5 |
| channel 1: slots B2, B6 |
| channel 2: slots B3, B7 |
| channel 3: slots B4, B8 |
The following table shows the memory populations and operating frequencies for the supported configurations.
54
