Fujitsu MBA3147RC Verify errors recovered without delays page 05, code, TSD ETC TMC Lbin

5.2 Log Parameters

•Verify errors recovered without delays (page 05, code 0000)

Table 5.39 Verify errors recovered without delays (page 05, code 0000)

Byte	Bit	7	6	5	4	3		2	1	0
4		(MSB)		X'0000' (Parameter code)
5
				(Errors Recovered Without Delays)						(LSB)
6		DU	DS	TSD	ETC		TMC		LBIN	LP
		0	0	0	0	0	0		0	0
7				X'04' (Parameter Length)
8		(MSB)
9					Counter Value
10
11										(LSB)

The Counter Value indicates the count of all recovered verify errors that would not be reported to the initiator during verify operations, because no delay is incurred.

•Verify errors recovered with possible delays (page 05, code 0001)

Table 5.40 Verify errors recovered with possible delays (page 05, code 0001)

Byte	Bit	7	6	5	4	3		2	1	0
4		(MSB)		X'0001' (Parameter code)
5
				(Errors Recovered With Possible Delays)						(LSB)
6		DU	DS	TSD	ETC		TMC		LBIN	LP
		0	0	0	0	0	0		0	0
7				X'04' (Parameter Length)
8		(MSB)
9					Counter Value
10
11										(LSB)

The Counter Value indicates the count of all recovered verify errors that would not be reported to the initiator during verify operations, because possible delay is incurred.

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