HP Integrity Superdome and 9000 Superdome sx2000 manual Processors, Cell Memory System

Processors

There are several Itanium and PA-RISC processor families supported by the processors are already installed on the cell board. All processors require that a minimum firmware version be installed. For the processors supported, seeTable 1-2.

Table 1-2 Supported Processors and Minimum Firmware Versions

Processor Family

Intel ® Itanium® single-core processors with 9 MB cache

Intel ® Itanium® dual-core processors with 18 MB cache

Intel ® Itanium® dual-core processors with 24 MB cache PA-8900 dual-core processor with 64 MB cache

Intel ® Itanium ® dual-core 9100 series processors with 18 MB cache

Minimum Firmware Version	Core Frequency
4.3e (IPF SFW 004.080.000)	1.6 GHz
5.5d (IPF SFW 005.024.000)	1.6 GHz
5.5d (IPF SFW 005.024.000)	1.6 GHz
PDC_FW 042.009.000	1.1 GHz
8.6d (IPF SFW 009.022.000)	1.6 GHz

Intel ® Itanium ® dual-core 9100 series processors with 24 8.6d (IPF SFW 009.022.000)	1.6 GHz
MB cache

Rules for Processor Mixing

•Processor families cannot be mixed on a cell board or within a partition

•Processor frequencies cannot be mixed on a cell board or within a partition

•Cache sizes cannot be mixed on a cell board or within a partition

•Major processor steppings cannot be mixed on a cell board or within a partition

•Full support for Itanium and PA-RISC processors within the same complex but in different partitions

Cell Memory System

Each cell in the sx2000 system has its own independent memory subsystem. This memory subsystem consists of four logical memory subsystems that achieve a combined bandwidth of 17 GB/s peak, 14-16 GB/s sustained. This cell is the first of the Superdome designs to support the use of DDR I/O DRAM. These DIMMs are to be based on the DDR-II protocol, and the cell design supports DIMM capacities of 1, 2, or 4 GB using monolithic DRAMs. Nonmonolithic, (stacked) DRAMS are not supported on the sx2000. The additional capacitive load and requirement for additional chip selects is not accommodated by the new chipset. All DIMMs used in the sx2000 are compatible with those used in other new CEC platforms. However other platforms can support DIMMs based on nonmonolithic DRAMs that are incompatible with the sx2000. Cell memory is illustrated in Figure 1-10.

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