DRAM Erasure
A common cause of a correctable memory error is a DRAM failure; the ability to correct this type of memory failure in hardware is called chip kill. Address or control bit failure is a common cause. Chip kill ECC schemes have added hardware logic that enables them to detect and correct more than a
Double chip kill is an extension to memory chip kill that enables the system to correct multiple ECC errors in an ECC code word. Double chip kill is also known as DRAM erasure.
DRAM erasure is invoked when the number of correctable memory errors exceeds a threshold. It can be invoked on a memory subsystem, bus, rank or bank. PDC tracks the errors on the memory subsystem, bus, rank and bank in addition to the error information it tracks in the PDT.
PDC Functional Changes
There are three primary threads of control in the processor dependent code (PDC): the bootstrap, the errors code, and the PDC procedures. The bootstrap is the primary thread of control until the OS is launched. The boot console handler (BCH) acts as a user interface for the bootstrap, but can also be used to diagnose problems with the system. The BCH can call the PDC procedures but this explicit capability is only available in MFG mode through the Debug menu.
The PDC procedures are the primary thread of control once the OS launches. Once the OS launches, the PDC code is only active when the OS calls a PDC procedure or there is an error that calls the error code. Normally, the error thread of control returns control back to the OS through OS_HPMC, OS_TOC or RFI (LPMC or CMCI). In some cases, the HPMC or MCA handler halts the cell or partition.
If a correctable memory error occurs during run time, the new chipset logs the error and corrects it in memory (reactive scrubbing). Diagnostics periodically call PDC_PAT_MEM (Read Memory Module State Info) to read the errors logs. When this PDC call is made, system firmware updates the PDT, and deletes entries older than 24 hours in the structure that counts how many errors have occurred for each memory subsystem, bus, rank or bank. When the counts exceed the thresholds, PDC invokes DRAM erasure on the appropriate memory subsystem, bus, rank or bank. Invoking DRAM erasure does not interrupt the operation of the OS.
When PDC invokes DRAM erasure, the information returned by PDC_PAT_MEM (Read Memory Module State Info) indicates the scope of the invocation and provides information to enable diagnostics to determine why it was invoked. PDC also sends IPMI events indicating that DRAM erasure is in use. When PDC invokes DRAM erasure, the correctable errors that caused DRAM erasure are removed from the PDT. Because invoking DRAM erasure increases the latency of memory accesses and reduces the ability of ECC to detect multibit errors, you must notify the customer that the memory subsystem must be serviced. HP recommends that the memory subsystem be serviced within a month of invoking DRAM erasure on a customer machine.
The thresholds for invoking DRAM erasure are incremental, so that PDC invokes DRAM erasure on the smallest part of memory subsystem necessary to protect the system against another bit error.
Platform Dependent Hardware
The platform dependent hardware (PDH) includes functionality that is required by both system and management firmware. The PDH provides the following features:
•An interface that passes multiple forms of information between system firmware and the MP on the SBC by the platform dependent hardware controller (PDHC, on the PDH daughter card).
•Flash EPROM for PDHC boot code storage.
•PDHC SRAM for operational instruction and data storage.
36 Overview
