KS57C2308/P2308/C2316/P2316 ADDRESS SPACES
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++ PROGRAMMING TIP — Defining Vectored Interrupts
The following examples show you several ways you can define the vectored interrupt and instruction reference
areas in program memory:
1. When all vector interrupts are used:
ORG 0000H
VENT0 1,0,RESET ;EMB ← 1, ERB ← 0; Jump to RESET address by RESET
VENT1 0,0,INTB ;EMB ← 0, ERB ← 0; Jump to INTB address by INTB
VENT2 0,0,INT0 ;EMB ← 0, ERB ← 0; Jump to INT0 address by INT0
VENT3 0,0,INT1 ;EMB ← 0, ERB ← 0; Jump to INT1 address by INT1
VENT4 0,0,INTS ;EMB ← 0, ERB ← 0; Jump to INTS address by INTS
VENT5 0,0,INTT0 ;EMB ← 0, ERB ← 0; Jump to INTT0 address by INTT0
2. When a specific vectored interrupt such as INT0, and INTT0 is not used, the unused vector interrupt
locations must be skipped with the assembly instruction ORG so that jumps will address the correct locations:
ORG 0000H
VENT0 1,0,RESET ;EMB ← 1, ERB ← 0; Jump to RESET address by RESET
VENT1 0,0,INTB ;EMB ← 0, ERB ← 0; Jump to INTB address by INTB
ORG 0006H ;INT0 interrupt not used
VENT3 0,0,INT1 ;EMB ← 0, ERB ← 0; Jump to INT1 address by INT1
VENT4 0,0,INTS ;EMB ← 0, ERB ← 0; Jump to INTS address by INTS
ORG 000CH ;INTT0 interrupt not used
ORG 0010H
3. If an INT0 interrupt is not used and if its corresponding vector interrupt area is not fully utilized, or if it is not
written by a ORG instruction in Example 2, a CPU malfunction will occur:
ORG 0000H
VENT0 1,0,RESET ;EMB ← 1, ERB ← 0; Jump to RESET address by RESET
VENT1 0,0,INTB ;EMB ← 0, ERB ← 0; Jump to INTB address by INTB
VENT3 0,0,INT1 ;EMB ← 0, ERB ← 0; Jump to INT1 address by INT0
VENT4 0,0,INTS ;EMB ← 0, ERB ← 0; Jump to INTS address by INT1
VENT5 0,0,INTT0 ;EMB ← 0, ERB ← 0; Jump to INTT0 address by INTS
ORG 0010H
General-purpose ROM area
In this example, when an INTS interrupt is generated, the corresponding vector area is not VENT4 INTS, but
VENT5 INTT0. This causes an INTS interrupt to jump incorrectly to the INTT0 address and causes a CPU
malfunction to occur.