+ Programming TIP Defining Vectored Interrupts | Samsung KS57C2308

KS57C2308/P2308/C2316/P2316	ADDRESS SPACES

+PROGRAMMING TIP — Defining Vectored Interrupts

The following examples show you several ways you can define the vectored interrupt and instruction reference areas in program memory:

1.When all vector interrupts are used:

ORG 0000H

VENT0	1,0,RESET	;	EMB ← 1, ERB ← 0; Jump to RESET address by RESET
VENT1	0,0,INTB	;	EMB ← 0, ERB ← 0; Jump to INTB address by INTB
VENT2	0,0,INT0	;	EMB ← 0, ERB ← 0; Jump to INT0 address by INT0
VENT3	0,0,INT1	;	EMB ← 0, ERB ← 0; Jump to INT1 address by INT1
VENT4	0,0,INTS	;	EMB ← 0, ERB ← 0; Jump to INTS address by INTS
VENT5	0,0,INTT0	;	EMB ← 0, ERB ← 0; Jump to INTT0 address by INTT0

2.When a specific vectored interrupt such as INT0, and INTT0 is not used, the unused vector interrupt locations must be skipped with the assembly instruction ORG so that jumps will address the correct locations:

ORG	0000H
VENT0	1,0,RESET	;	EMB ← 1, ERB ← 0; Jump to RESET address by RESET
VENT1	0,0,INTB	;	EMB ← 0, ERB ← 0; Jump to INTB address by INTB
ORG	0006H	; INT0 interrupt not used
VENT3	0,0,INT1	;	EMB ← 0, ERB ← 0; Jump to INT1 address by INT1
VENT4	0,0,INTS	;	EMB ← 0, ERB ← 0; Jump to INTS address by INTS
ORG	000CH	; INTT0 interrupt not used
ORG	0010H

3.If an INT0 interrupt is not used and if its corresponding vector interrupt area is not fully utilized, or if it is not written by a ORG instruction in Example 2, a CPU malfunction will occur:

ORG 0000H

VENT0	1,0,RESET	;	EMB ← 1, ERB ← 0; Jump to RESET address by RESET
VENT1	0,0,INTB	;	EMB ← 0, ERB ← 0; Jump to INTB address by INTB
VENT3	0,0,INT1	;	EMB ← 0, ERB ← 0; Jump to INT1 address by INT0
VENT4	0,0,INTS	;	EMB ← 0, ERB ← 0; Jump to INTS address by INT1
VENT5	0,0,INTT0	;	EMB ← 0, ERB ← 0; Jump to INTT0 address by INTS
ORG	0010H

General-purpose ROM area

In this example, when an INTS interrupt is generated, the corresponding vector area is not VENT4 INTS, but VENT5 INTT0. This causes an INTS interrupt to jump incorrectly to the INTT0 address and causes a CPU malfunction to occur.

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Samsung KS57C2308 manual + Programming TIP Defining Vectored Interrupts

Contents

Overview Product Overview Watch Timer PinsBit Basic Timer Bit Timer/Counter Block Diagram KS57C2308 INT2 INT4INT0 INT1 Test Test signal input must be connected to V SS PIN Circuit Diagrams Pin Circuit Type E P4, P5 Vector Addresses Address SpacesOverview General-Purpose Program Memory PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 GENERAL-PURPOSE Memory AreasVector Address Area EMB ERB + Programming TIP Defining Vectored Interrupts Instruction Reference Area + Programming TIP Using the REF Look-Up Table Data Memory RAM Working Registers Memory Banks 0, 1,F80H-FFFH Data Memory Addressing Modes RMCL0 @HL,A Incs + Programming TIP Clearing Data Memory Banks 0Ramclr SMB RMCL1 @HL,A Incs SMB Working Register Map Working Registers Paired Working Registers Working Register Banks Special-Purpose Working Registers Incs WX,EA YZ,EA POP + Programming TIP Selecting the Working Register AreaINT0 Push SRB + Programming TIP Initializing the Stack Pointer Stack Pointer SPSP3 SP2 SP1 SP7 SP6 SP5 SP4 Interrupt Routines Push OperationsPush Instructions Call Instructions Iret Instructions POP OperationsPOP Instructions RET and Sret Instructions BSC Register Organization Name Address Bit MSB LSB FB0H IS1 IS0 EMB ERB FB1H SC2 SC1 SC0 Program Counter PC IS1 IS0 Interrupt Status Flag Bit SettingsInterrupt Status Flags IS0, IS1 EMB Flag EMB + Programming TIP Using the EMB Flag to Select Memory Banks HL,EA ERB Flag ERB Valid Carry Flag Manipulation Instructions Operation Type Skip Condition Flags SC2, SC1, SC0Carry Flag C Band HL,#0AAHADC EA,HL Address Spaces Addressing Modes RAM Address Structure + Programming TIP Initializing the EMB and ERB Flags Reset Bitr EMBEMB and ERB Initialization Values EMB-Independent Addressing Enable Memory Bank SettingsEMB = Select Memory Bank SMB Instruction Select Bank Register SB Bank Mapping Direct and Indirect AddressingBIT Addressing Bit Indirect Addressing Bdata EQU 8EH SMB @HL@WL Adata EQU Sret Decs Comp RET Bdata EQUHL,#BDATA WX,#ADATA Comp @WL Cpse @HL SMB HL,#BDATA WX,#ADATA Trans @WL Bit Indirect Addressing ExampleHL,#BDATA WX,#ADATA Trans @WL Xchd @HL Bdata EQU 8EH SMB EA,P4 EA,P4SMB ADATA,EA BDATA,EA SMB HL,#ADATA EA,@HL HL,#ADATA EA,@HL MAP for Hardware Registers Memory MAP I/O Map for Memory Bank Addressing Mode Register Bit Fbch INT C IET0 IRQT0 FB7H ScmodFB8H INT a IE4 IRQ4 IEB Irqb Fbah INT B IEW Irqw Register Descriptions Register Description Format Bit Identifier Bmod Basic Timer Mode RegisterRead/Write Bit Addressing Basic Timer Restart Bit Clock Source and Frequency Selection Control Bits Clmod Clock Output Mode RegisterFD0H IE1 IRQ1 IE0 IRQ0 IE0, 1, IRQ0, 1 INT0, 1 Interrupt Enable/Request FlagsFbeh IE2 IRQ2 IE2, IRQ2 INT2 Interrupt Enable/Request FlagsFbfh IE4 IRQ4 IEB Irqb IE4, IRQ4 INT4 Interrupt Enable/Request FlagsIEB, Irqb Intb Interrupt Enable/Request Flags FB8H IES Irqs IES, Irqs Ints Interrupt Enable/Request FlagsInts Interrupt Enable Flag Fbdh IET0 IRQT0 IET0, IRQT0 INTT0 Interrupt Enable/Request FlagsINTT0 Interrupt Enable Flag Fbch IEW Irqw IEW, Irqw Intw Interrupt Enable/Request FlagsIntw Interrupt Enable Flag Fbah FB4H IMOD0 External Interrupt 0 INT0 Mode RegisterExternal Interrupt Mode Control Bits External Interrupt 1 Edge Detection Control Bit IMOD1 External Interrupt 1 INT1 Mode RegisterFB5H IMOD1.0 External Interrupt 2 Edge Detection Selection Bit IMOD2 External Interrupt 2 INT2 Mode RegisterFB6H IMOD2.2 IMOD2.1 IMOD2.0 IME Interrupt Master Enable BitIPR Interrupt Priority Register FB2H Read/Write Bit Addressing LCD Bias Selection Bit LCD Clock Output Disable/Enable BitLcon LCD Output Control Register F8EH Duty and Bias Selection for LCD Display Lmod LCD Mode RegisterF8DH, F8CH LCD Clock Lcdck Frequency Selection Bits CPU Clock Frequency Selection Bits Pcon Power Control RegisterRead/Write Bit Addressing CPU Operating Mode Control Bits FB3H FE9H, FE8H PMG1 Port I/O Mode Flags Group 1 Port 3 PM7 PM5 PM4 PM2 PMG2 Port I/O Mode Flags Group 2 Port 2, 4, 5,FEDH, Fech FD7H, FD6H PNE N-Channel Open-Drain Mode Register SC2-SC0 SC1 IS1 IS0 EMB ERB PSW Program Status WordFB1H, FB0H PUR7 PUR6 PUR5 PUR4 PUR3 PUR2 PUR1 PUR0 Pumod Pull-Up Resistor Mode RegisterFDDH, Fdch 1Bit Scmod System Clock Mode Control RegisterFB7H FE1H, FE0H Smod Serial I/O Mode Register Clear Counter and Resume Counting Control Bit TMOD0 Timer/Counter 0 Mode Register F91H, F90HTimer/Counter 0 Input Clock Selection Bits Enable/Disable Timer/Counter 0 Bit Bit3 TOE Timer Output Enable Flag RegisterTimer/Counter 0 Output Enable Flag TOE0 Wdtcf Wdflag Watchdog Timer Counter Clear Flag RegisterWatchdog Timer Counter Clear Flag F9AH 5AH Wdmod Watchdog Timer Mode Register F99H, F98HWatchdog Timer Enable/Disable Control Wdmod Wmod Watch Timer Mode Register F89H, F88H SAM47 Instruction SET Instruction SET Features Instruction Reference Area Bitr EMB Reducing Instruction Redundancy Instructions Which Affect the Carry Flag Flexible Bit ManipulationInstructions Which Have Skip Conditions SBC A,@HL ADC and SBC Instruction Skip ConditionsADC A,@HL Register Identifiers Full Register Name Symbols and Conventions Data Type SymbolsInstruction Operand Notation Symbol Definition @HL @WX @WL Opcode DefinitionsOpcode Definitions Direct Register Opcode Definitions Indirect Register HIGH-LEVEL Summary EA,RR IdleStop Cpse DA,A XCHEA,DA Xchi @HL SBC @HL COMADC @HL ADS Bitr Btstz Binary Code Summary SCF RCF CCF First Byte Condition PC13-8 ← SP + 1 SP Ra,#im Ra ← im RR,#imm RR ← imm EA,RR EA ← EA XOR RR EA,RR EA ← EA and RREA,RR EA ← EA or RR ← a + HL + C Skip if C = FB0H-FBFH FF0H-FFFH Second Byte Bit Addresses LDB Instruction Descriptions Operand Binary Code Operation Notation ADC Add With CarryADC Operation Operand Operation Summary Bytes Cycles #8H ← 8H JPS YYY ADS Add And Skip On OverflowADS ADS EA,HL EA ← 0C3H + 12H = 0D5H Logical Band C,P1.@L Band Bit LogicalBand SMB Band Band @H+FLAG Flag EQU Bitr P2.0 Bitr Bit ResetBitr FF1H-FF9H Incs BP2 BP2 Bitr Bits P2.0 Bits Bit SetBits BP2 Bits BOR BOR Bit Logical or BOR @H+FLAG LABEL3 Btsf Bit Test and Skip on FalseBtsf LABEL2 RET Incs BP2 BP2 Btsf Btst Btst Bit Test and Skip on True BP2 Btst BP2 Btstz Btstz Bit Test and Skip on True Clear BitBtstz Bits @H+FLAG Btstz @H+FLAG RCF Bxor C,P1.0 Bxor Bit Exclusive orBxor Bxor @H+FLAG Operand Operation Summary Bytes Cycles Call Call ProcedureCall Operation 0FFH 0FEH EMB, ERB 0FDH 0FCH 0FBH 0FAH Calls Call Procedure ShortCalls Operation Calls Play CCF CCF Complement Carry Flag COM a COM Complement AccumulatorCOM Cpse EA,HL RET Cpse Compare and Skip if EqualCpse Call PLAY1 Decs Decrement and Skip on BorrowDecs Decs HL DI Disable Interrupts EI Enable Interrupts Idle NOP Idle Idle OperationIdle Incs @HL Incs Increment and Skip on CarryIncs SC2 SC1 SC0 Iret Return From InterruptIret IS1 IS0 EMB ERB Jump to direct address 14 bits JP JumpJP Operation ADR14 Jump direct in page 12 bits JPS Jump ShortJPS Operation ADR12 JR Jump Relative Very Short JPS YYY XXX LD JR KKJPS AAA BBB CCC DDD EA,WX ADS WX,EA LD Load Description Operand Binary Code Operation Notation Instruction Operation Description and Guidelines Examples Instruction Operation Description and Guidelines LDB LDB Load Bit LDB @H+FLAG,C FlagLDB @H+FLAG Flag EQU 20H.3 RCF Display LDC LDC Load Code ByteLDC Call Display JPS Main ORG 01FFH LDC Display LDORG 01FDH LDD Operation LDD Load Data Memory and Decrement HL,#2FH LDI @HL LDI Load Data Memory and IncrementLDI Operation Stop NOP NOP No OperationNOP Or EA,@HL Or Logical or POP HL POP Pop From StackPOP Push HL Push Push Onto StackPush RCF RCF Reset Carry Flag Operand Operation Summary Bytes Cycles Memc Reference code REF Reference InstructionOperation AAA LD BBB EA,#FFH CCC Tcall SUB1 DDD TJP SUB2BBB EA,#FFH CCC Call SUB1 DDD SUB2 TJP SUB2 ORG Opcode Symbol InstructionHL,#0FH Tcall SUB1 PSW ← EMB,ERB RET Return From SubroutineRET RRC a RRC Rotate Accumulator Right Through CarryRRC RCF SBC EA,HL SBC Subtract With CarrySBC SCF SBC EA,HL #8H SCF SBS EA,HL SBS SubtractSBS RCF SBS EA,HL SCF SCF Set Carry Flag Format Binary Code Operation Notation SMB Select Memory BankSMB Addresses Register Areas Bank SRB ERB Setting SRB Settings Selected Register BankSRB Select Register Bank Sret Sret Return From Subroutine and Skip Stop Stop Stop Operation VENTn Vent Load EMB, ERB, and Vector Address VENTn Example The instruction sequence XCH EA,@HL XCH Exchange a or EA with Nibble or ByteXCH YYY Xchd @HL Xchd Exchange and DecrementXchd Operation YYY Xchi @HL Xchi Exchange and IncrementXchi Operation HL,#2FH XOR EA,HL XOR Logical Exclusive orXOR SAM47 Instruction SET Oscillator Circuits Interrupts Power-Down Page CPU Clock Notation Oscillator Circuits Clock Control Registers Using a Subsystem Clock STO Clock Circuit Diagram Subsystem Oscillator Circuits Main System Oscillator Circuits SCMOD.0 = Power Control Register PconPcon Bit Settings Resulting CPU Operating Mode PCON.1 PCON.0 Instruction Cycle Times + Programming TIP Setting the CPU ClockPCON,A Fx Oscillation Fxt Oscillation System Clock Mode Register ScmodFB7H SCMOD.3 SCMOD.2 SCMOD.0 Scmod SCMOD.3 SCMOD.2 SCMOD.0 Oscillator CIRCUITSKS57C2308/P2308/C2316/P2316 KS57C2308/P2308/C2316/P2316OSCILLATOR Circuits Switching the CPU Clock Elapsed Machine Cycles During CPU Clock Switch Clock Source Frequency Clock Output Mode Register ClmodResult of CLMOD.3 Setting CLMOD.1 CLMOD.0 Clock Output Circuit Clock Output Procedure CLMOD,A + Programming TIP CPU Clock Output to the CLO PinPMG2,EA INTB, INTT0, Ints Interrupt Types and Corresponding Port Pins Interrupt NameInterrupts INT0, INT1, INT4 Multiple Interrupts Power-Down Mode ReleaseVectored Interrupts Software-Generated Interrupts Interrupt Execution Flowchart Interrupt Control Circuit Diagram Two-Level Interrupt Handling Multiple Interrupts Multi-Level Interrupt Handling Interrupt Priority Register IPR Standard Interrupt Priorities Default PriorityInterrupt Priority Register Settings Result of IPR Bit Setting IMOD1 IMOD1.0 IMOD0 IMOD0.3 IMOD0.1 IMOD0.0 IRQ0 IRQ1 Edge IMOD1 External INTERRUPT0 and INTERRUPT1 Mode RegistersINT0 Noise Filter Edge Clock Selector INT1 IMOD0 FB6H IMOD2.2 IMOD2.1 IMOD2.0 External Interrupt 2 Mode Register IMOD2IMOD2 Register Bit Settings Effect of IMOD2 Settings Circuit Diagram for INT2 and KS0-KS7 Pins IME IPR.2 IPR.1 IPR.0 Interrupt Flags Interrupt Request Flags IRQx Iret INT4 Bitr IRQ4 + Programming TIP Enabling the Intb and INT4 InterruptsIntb Btstz Irqb POWER-DOWN CPU Stop Idle Timing When Idle Mode is Released by Reset Idle Mode Timing Diagrams Timing When Stop Mode is Released by Reset Stop Mode Timing Diagrams SMB Bitr Irqw IRQ2 Bits IEW IE2 CLKS1 Call Watdis Keyclk Call MA2SUBP2,EA IMOD2,A Port PIN Configuration for POWER-DOWN SEG0-SEG23 Recommended Connections for Unused PinsP3.1/LCDSY P3.0/LCDCK POWER-DOWN Timing for Oscillation Stabilization After Reset Clocks Hardware Register Values After ResetProgram Status Word PSW Data Memory RAM LCD Driver/Controller Basic TimerTimer/Counters 0 Watchdog Timer KS57C2308/P2308/C2316/P2316 10 I/O Ports Port Mode FlagsPull-Up Resistor Mode Register Pumod Channel Open-Drain Mode Register PNE P6,EA Pumod ID Port Mode Flags PM FlagsPULL-UP Resistor Mode Register Pumod PIN Addressing for Output Port Channel OPEN-DRAIN Mode Register PNELMOD.7 and LMOD.6 Setting for Port 8 Output Control LCD Output Segments Bit Output Pins 1FBH SEG27 SEG24SEG25 1FAH SEG26 Port 0 Circuit Diagram Port 0 Circuit Diagram IMOD0 IMOD1 Port 1 Circuit Diagram Port 2 Circuit Diagram Port 2 Circuit Diagram Port 3 and 6 Circuit Diagram Port 3 and 6 Circuit Diagram Port 4 and 5 Circuit Diagram Port 4 and 5 Circuit Diagram Port 7 Circuit Diagram Port 7 Circuit Diagram 10-12 KS57C2308/P2308/C2316/P2316 Timers and TIMER/COUNTERS Oscillation Stabilization Interval Control Interval Timer FunctionWatchdog Timer Function Wdtcf Basic Timer Register Overview Type Description SizeAddressing Reset Name Mode RAM BMOD.3 Basic Timer Mode Register BmodBasic Timer Mode Register Bmod Organization Basic Timer Input Clock Interval Time Basic Timer Operation Sequence Basic Timer Counter Bcnt + Programming TIP Using the Basic Timer Bmod Watchdog Timer Mode Register WdmodWatchdog Timer Counter Wdcnt Watchdog Timer Counter Clear Flag Wdtcf BMOD,A Main Bits Wdtcf + Programming TIP Using the Watchdog TimerReset Bits EMB SMB TC0 Function Summary BIT TIMER/COUNTER 0 TC0 TC0 Component Summary TC0 Register Overview Type Description Size TC0 Circuit Diagram Disable Timer/Counter TC0 ENABLE/DISABLE ProcedureEnable Timer/Counter TC0 Operation Sequence TC0 Programmable TIMER/COUNTER Function TCL0 Edge Detection TMOD0 Settings for TCL0 Edge DetectionTC0 Event Counter Function TMOD0.5 TMOD0.4 Bits TOE0 + Programming TIP TC0 Signal Output to the TCLO0 PinTC0 Clock Frequency Output TREF0,EA EA,#4CH TMOD0,EA TREF0,EA EA,#0CH TMOD0,EA TC0 External Input Signal DividerTC0 Serial I/O Clock Generation TC0 Mode Register TMOD0 + Programming TIP Restarting TC0 Counting Operation TMOD0.6, TMOD0.5, and TMOD0.4 Bit SettingsTMOD0.6 TMOD0.5 TMOD0.4 Resulting Counter Source and Clock Frequency TC0 Counter Register TCNT0 TC0 Timing Diagram TC0 Output Latch TOL0 TC0 Output Enable Flag TOE0TC0 Reference Register TREF0 MSB LSB TREF0,EA + Programming TIP Setting a TC0 Timer Interval Clock Source Generation for LCD Controller Using a System or Subsystem Clock SourceReal-Time and Watch-Time Measurement Buzzer Output Frequency Generator Timing Tests in High-Speed ModeCheck Subsystem Clock Level Feature Watch Timer Circuit Diagram Watch Timer Mode Register Wmod Clock Btstz Irqw + Programming TIP Using the Watch TimerWMOD,EA Bits IEW Data BUS LCD Controller Driver LCD CONTROLLER/DRIVER LCD Circuit Diagram LCD Circuit Diagram LCD RAM Address Area P8.0-P8.7 LCON.0 and LMOD.3 Bit SettingsLCD Control Register Lcon LCON.0 LMOD.3 COM0-COM3 SEG0-SEG31 LMOD.3 LMOD.2 LMOD.1 LMOD.0 LCD Mode Register LmodLMOD.5 LMOD.4 LCD Voltage Dividing Resistors LCD Power Supply Static Mode BiasLCD Drive Voltage GND Voltage Dividing Resistor Circuit Diagrams LCD Common Signal Waveform Static Common COM Signals LCD Common Signal Waveform at 1/2 Bias 1/2, 1/3 Duty LCD Common Signal Waveform at 1/3 Bias 1/3, 1/4 Duty Select No-select Segment SEG SignalsSelect/No-Select Signals for LCD Static Display Mode SEG Select Non-select Select/No-Select Signals for LCD 1/2 Bias Display Mode 10. Select/No-select Bias Signals in 1/3 Bias Display Mode Select/No-Select Signals for LCD 1/3 Bias Display Mode COM0 SEG11 SEG12 VLC0 VSS +VLCD 0 Vlcd 11. LCD Signal Waveforms in Static Mode 12. LCD Connection Example in Static Mode COM0 COM1 SEG9 13. LCD Signal Waveforms at 1/2 Duty, 1/2 Bias 14. LCD Connection Example at 1/2 Duty, 1/2 Bias COM0 COM1 COM2 SEG12 15. LCD Signal Waveforms at 1/3 Duty, 1/2 Bias 16. LCD Connection Example at 1/3 Duty, 1/2 Bias 17. LCD Signal Waveforms at 1/3 Duty, 1/3 Bias 18. LCD Connection Example at 1/3 Duty, 1/3 Bias COM0 COM1 COM2 COM3 SEG13 19. LCD Signal Waveforms at 1/4 Duty, 1/3 Bias 20. LCD Connection Example at 1/4 Duty, 1/3 Bias 12-24 Serial I/O Operation Sequence Serial I/O Interface Serial I/O Interface Circuit Diagram SMOD.2 Serial I/O Mode Register SmodSMOD.0 SMOD.1 SIO Timing in Transmit/Receive Mode Serial I/O Timing Diagrams SBUF,EA EA,#4FH SMOD,EA Serial I/O Buffer Register SbufSBUF,EA EA,#0EEH SMOD,EA Bitr EMB EA,TDATA Bits SMOD.3 SBUF,EA EA,#8FH SMOD,EABits IES Ints Push XCH EA,SBUF High Speed SIO Transmission SBUF,EA EA,#0FH SMOD,EA 13-8 Miscellaneous Timing Waveforms Standard Electrical CharacteristicsStop Mode Characteristics and Timing Waveforms Electrical Data Absolute Maximum Ratings Parameter Symbol Conditions Rating UnitsD.C. Electrical Characteristics Parameter Symbol Conditions Min Typ Max Units Output low Stop mode DD = 5 V ± 10% CPU = fx/4, Scmod = 0100B D.C. Electrical Characteristics Concluded Main System Clock Oscillator Characteristics Input/Output Capacitance Subsystem Clock Oscillator CharacteristicsParameter Symbol Condition Min Typ Max Units Input Width A.C. Electrical Characteristics Released by Reset 17/fx Time Released by interrupt Parameter Symbol Conditions Min Typ Max Unit Timing Waveforms A.C. Timing Measurement Points Except for XIN and Xtin TCL0 Timing 10. Serial Data Transfer Timing Mechanical Data QFP-1420C Package Dimensions 15-2 16 KS57P2308/P2316 OTP KS57P2308/KS57P2316 Test Operating Mode CharacteristicsREG 16-4 16-5 KS57P2308/P2316 OTPKS57C2308/P2308/C2316/P2316 16-7 16-8 16-9 16-10 Timing Waveforms 16-12 16-13 11. Serial Data Transfer Timing 12. OTP Programming Algorithm KS57P2308/P2316 OTP KS57C2308/P2308/C2316/P2316 16-16 HEX2ROM ShineSama Assembler SASM57 Smds Product Configuration SMDS2+ 17-2 TB572308A/16A Target Board SMDS2/SMDS2+ Xtal MDS Stop LED XTIIdle LED DIP Pin Connectors for TB572308A/16A KS57 Series Mask ROM Order Form Page Order Quantity and Delivery Schedule KS57 Series Request for Production AT Customer RiskRisk Order Information Customer Risk Order AgreementPage Customer Checksum Company Name Signature Engineer KS57C2308 Mask Option Selection FormAttachment Check one PromPage KS57C2316 Mask Option Selection Form KS57 Series OTP Factory Writing Order Form 1/2 + What is the purpose of this order?Page If so, how much will you be ordering? PCS KS57P2308 OTP Factory Writing Order Form 2/2Device Number + Are you going to continue ordering this device?Page KS57P2316 OTP Factory Writing Order Form 2/2