MEMORY MAPKS57C2308/P2308/C2316/P2316

WMOD — Watch Timer Mode Register

F89H, F88H

Bit

Identifier

RESET Value

Read/Write

Bit Addressing

.7

.6

.5–.4

.3

.2

7

6

5

4

3

2

1

0

.7

"0"

.5

.4

.3

.2

.1

.0

 

 

 

 

 

 

 

 

0

0

0

0

(note)

0

0

0

W

W

W

W

R

W

W

W

8

8

8

8

1

8

8

8

Enable/Disable Buzzer Output Bit

0Disable buzzer (BUZ) signal output

1Enable buzzer (BUZ) signal output

Bit 6

0 Always logic zero

Output Buzzer Frequency Selection Bits

0

0 2 kHz buzzer (BUZ) signal output

01 4 kHz buzzer (BUZ) signal output

10 8 kHz buzzer (BUZ) signal output

1

1 16 kHz buzzer (BUZ) signal output

XTIN Input Level Control Bit

0Input level to XTIN pin is low; 1-bit read-only addressable for test

1Input level to XTIN pin is high; 1-bit read-only addressable for test

Enable/Disable Watch Timer Bit

0Disable watch timer and clear frequency dividing circuits

1Enable watch timer

.1

Watch Timer Speed Control Bit

0Normal speed; set IRQW to 0.5 seconds

1High-speed operation; set IRQW to 3.91 ms

.0

Watch Timer Clock Selection Bit

0Select the system clock (fxx/128) as the watch timer clock

1Select a subsystem clock as the watch timer clock

NOTE: RESET sets WMOD.3 to the current input level of the subsystem clock, XTIN. If the input level is high, WMOD.3 is set to logic one; if low, WMOD.3 is cleared to zero along with all the other bits in the WMOD register.

4-32

Page 74
Image 74
Samsung KS57C2308 manual Wmod Watch Timer Mode Register F89H, F88H