Samsung KS57C2308

KS57C2308/P2308/C2316/P2316 LCD CONTROLLER/DRIVER

12-11

SEGMENT (SEG) SIGNALS

The 32 LCD segment signal pins are connected to corresponding display RAM locations at 1E0H–1FFH. Bits 0–3

of the display RAM are synchronized with the common signal output pins COM0, COM1, COM2, and COM3.

When the bit value of a display RAM location is "1", a select signal is sent to the corresponding segment pin.

When the display bit is "0", a “no-select” signal is sent to the corresponding segment pin. Each bias has select

and no-select signals.

Table 12-7. Select/No-Select Signals for LCD Static Display Mode

SEG Select No-select

COM VLC0/VSS VSS/VLC0

VSS/VLC0 –VLC0/ + VLC0 0 V/ 0 V

T: LCDCK

COM

VLC0

SEG

SELECT

NO-SELECT VLC0

Figure 12-8. Select/No-select Bias Signals in Static Display Mode

Contents

Main 1 OVERVIEW OTP FEATURES KS57C2308/P2308/C2316/P2316 PRODUCT OVERVIEW 1-3 BLOCK DIAGRAM Figure 1-1. KS57C2308/C2316 Simplified Block Diagram PIN ASSIGNMENTS KS57C2308 KS57C2316 Figure 1-2. KS57C2308/C2316 80-QFP Pin Assignment Diagram PIN DESCRIPTIONS Page PIN CIRCUIT DIAGRAMS Figure 1-3. Pin Circuit Type A Figure 1-4. Pin Circuit Type A-1 (P1, P0.0, P0.3) Figure 1-5. Pin Circuit Type C Figure 1-6. Pin Circuit Type D (P0.1, P0.2, P2, P3, P6, P7) Figure 1-7. Pin Circuit Type E (P4, P5) Figure 1-8. Pin Circuit Type H-15 (SEG/COM) Figure 1-9. Pin Circuit Type H-16 (P8) Figure 1-10. Pin Circuit Type B (RESET) 2 PROGRAM MEMORY (ROM) Page Page + + DATA MEMORY (RAM) Page + + ADDRESS SPACES KS57C2308/P2308/C2316/P2316 2-8 A Figure 2-4. Working Register Map Page Page + + STACK OPERATIONS + + Page Page BIT SEQUENTIAL CARRIER (BSC) + + PROGRAM COUNTER (PC) PROGRAM STATUS WORD (PSW) Page Page Page Page + + Page 3 ADDRESSING MODES KS57C2308/P2308/C2316/P2316 Figure 3-1. RAM Address Structure 3-2 Page Page Page Page Page + + ++ PROGRAMMING TIP 4-Bit Addressing Modes (Continued) Page + + ++ PROGRAMMING TIP 8-Bit Addressing Modes (Continued) 4 Page Page Page KS57C2308/P2308/C2316/P2316 MEMORY MAP Figure 4-1. Register Description Format 4-5 BMOD CLMOD IE0, 1, IRQ0, 1 INT0, 1 Interrupt Enable/Request Flags FBEH IE2 , IRQ2 IE4 , IRQ4 IEB, IRQB IES , IRQS IET0, IRQT0 INTT0 Interrupt Enable/Request Flags FBCH IEW , IRQW IMOD0 IMOD1 IMOD2 IPR LCON LMOD PCON PMG1 PMG2 PNE PSW PUMOD SCMOD SMOD TMOD0 TOE WDFLAG WDMOD WMOD Watch Timer Mode Register F89H, F88H 5 Page + + Page Page Page Page Page Page Page Page Page Page Page * Page Page Page Page Page Page Page Page Page ADC ADS ADS AND BAND BAND BITR BITR BITS BITS BOR Bit Logical OR BOR BTSF * BTSF Page BTST BTSTZ Bit Test and Skip on True; Clear Bit BTSTZ BXOR BXOR CALL Call Procedure CALLS Call Procedure (Short) CCF Complement Carry Flag COM Complement Accumulator CPSE Compare and Skip if Equal DECS DI Disable Interrupts EI Enable Interrupts IDLE Idle Operation INCS Increment and Skip on Carry IRET Return From Interrupt JP JPS JR Jump Relative (Very Short) * JR Page Page Page Page LDB Load Bit * LDB LDC Load Code Byte LDC LDD Load Data Memory and Decrement LDI Load Data Memory and Increment NOP No Operation OR Logical OR POP Pop From Stack PUSH Push Onto Stack RCF Reset Carry Flag Page Page Page RET RRC Rotate Accumulator Right Through Carry SBC Subtract With Carry SBC SBS Subtract SCF Set Carry Flag SMB Select Memory Bank SRB Select Register Bank SRET Return From Subroutine and Skip STOP Stop Operation VENT Load EMB, ERB, and Vector Address VENT XCH Exchange A or EA with Nibble or Byte XCHD Exchange and Decrement XCHI Exchange and Increment XOR Logical Exclusive OR Page Page Page 6 Page Page Page Page ++ PROGRAMMING TIP Setting the CPU Clock Page Page Page Page + + Page Page ++ PROGRAMMING TIP CPU Clock Output to the CLO Pin 7 Page Figure 7-1. Interrupt Execution Flowchart #@ @ Figure 7-2. Interrupt Control Circuit Diagram Page Page Page + + Page Page Figure 7-6. Circuit Diagram for INT2 and KS0KS7 Pins Page Page Page 8 Page IDLE MODE TIMING DIAGRAMS Figure 8-1. Timing When Idle Mode is Released by RESET Figure 8-2. Timing When Idle Mode is Released by an Interrupt STOP MODE TIMING DIAGRAMS Figure 8-3. Timing When Stop Mode is Released by RESET Figure 8-4. Timing When Main Stop or Main/Sub Stop Mode is Release by an Interrupt + + Page Page Page 9 Page Page Page 10 Page Page + + Page PORT 0 CIRCUIT DIAGRAM Figure 10-1. Port 0 Circuit Diagram PORT 1 CIRCUIT DIAGRAM Figure 10-2. Port 1 Circuit Diagram Page PORT 3 AND 6 CIRCUIT DIAGRAM Figure 10-4. Port 3 and 6 Circuit Diagram PORT 4 AND 5 CIRCUIT DIAGRAM Figure 10-5. Port 4 and 5 Circuit Diagram Page Page 11 BASIC TIMER (BT) Page Page Page + + Page + + 8-BIT TIMER/COUNTER 0 (TC0) Page Page Page Page Page Page Page Page Page Page Page + + WATCH TIMER Page TIMERS and TIMER/COUNTERS KS57C2308/P2308/C2316/P2316 11-24 fw fw/2 Figure 11-4. Watch Timer Circuit Diagram fw/2 (512 Hz) Page Page 12 LCD CONTROLLER/DRIVER KS57C2308/P2308/C2316/P2316 12-2 LCD CIRCUIT DIAGRAM ... Figure 12-2. LCD Circuit Diagram Page Page Page Page 12-7 Static and 1/3 Bias Figure 12-4. Voltage Dividing Resistor Circuit Diagrams Voltage Dividing Resistor Adjustment 1/2 Bias Static and 1/3 Bias (VLCD = 2.5 V at VDD = 5 V) Page Figure 12-6. LCD Common Signal Waveform at 1/2 Bias (1/2, 1/3 Duty) Figure 12-7. LCD Common Signal Waveform at 1/3 Bias (1/3, 1/4 Duty) Page Figure 12-9. Select/No-select Bias Signals in 1/2 Bias Display Mode Figure 12-10. Select/No-select Bias Signals in 1/3 Bias Display Mode Page Figure 12-12. LCD Connection Example in Static Mode 12-15 Page Figure 12-14. LCD Connection Example at 1/2 Duty, 1/2 Bias 12-17 Page Figure 12-16. LCD Connection Example at 1/3 Duty, 1/2 Bias 12-19 Page Figure 12-18. LCD Connection Example at 1/3 Duty, 1/3 Bias 12-21 Page Figure 12-20. LCD Connection Example at 1/4 Duty, 1/3 Bias 12-23 Page 13 SERIAL I/O INTERFACE KS57C2308/P2308/C2316/P2316 - Figure 13-1. Serial I/O Interface Circuit Diagram 13-2 Page SERIAL I/O TIMING DIAGRAMS Figure 13-2. SIO Timing in Transmit/Receive Mode Figure 13-3. SIO Timing in Receive-Only Mode ++ PROGRAMMING TIP Setting Transmit/Receive Modes for Serial I/O Page ++ PROGRAMMING TIP Setting Transmit/Receive Modes for Serial I/O (Continued) Page 14 OVERVIEW Page Page Page Page Page Page Page TIMING WAVEFORMS t Figure 14-3. Stop Mode Release Timing When Initiated By Interrupt Request t V Page Page ELECTRICAL DATA KS57C2308/P2308/C2316/P2316 Figure 14-10. Serial Data Transfer Timing 14-12 KS57C2308/P2308/C2316/P2316 MECHANICAL DATA 15-1 15 Figure 15-1. 80-QFP-1420C Package Dimensions 80-QFP-1420C Page 16 KS57P2308/KS57P2316 / Figure 16-1. KS57P2308/P2316 Pin Assignments (80-QFP) Page Page Page Page Page Page Page Page TIMING WAVEFORMS t Figure 16-4. Stop Mode Release Timing When Initiated By Interrupt Request t V Page Page KS57P2308/P2316 OTP KS57C2308/P2308/C2316/P2316 Figure 16-11. Serial Data Transfer Timing 16-14 KS57C2308/P2308/C2316/P2316 KS57P2308/P2316 OTP Figure 16-12. OTP Programming Algorithm 16-15 Page 17 17-2 Figure 17-1. SMDS Product Configuration (SMDS2+) SM1248A TB572308A/16A + Page Page 17-6 J101 40-PIN DIP CONNECTOR Figure 17-4. TB572308A/16A Adapter Cable for 80-QFP Package (KS57C2308/P2308/C2316/P2316) 0-PIN DIP CONNECTOR J102 4 KS57 SERIES MASK ROM ORDER FORM @ : Assembly site code, Y : Last number of assembly year, WW : Week of assembly @ YWW SEC @ YWW @ YWW Page KS57 SERIES REQUEST FOR PRODUCTION AT CUSTOMER RISK Page KS57C2308 MASK OPTION SELECTION FORM Page KS57C2316 MASK OPTION SELECTION FORM KS57 SERIES OTP FACTORY WRITING ORDER FORM (1/2) @ : Assembly site code, Y : Last number of assembly year, WW : Week of assembly @ YWW SEC @ YWW @ YWW Page KS57P2308 OTP FACTORY WRITING ORDER FORM (2/2) + + Page KS57P2316 OTP FACTORY WRITING ORDER FORM (2/2) + +