INTERRUPTS KS57C2308/P2308/C2316/P2316
7-8
++ PROGRAMMING TIP — Setting the INT Interrupt Priority
The following instruction sequence sets the INT1 interrupt to high priority:
BITS EMB
SMB 15
DI ;IPR.3 (IME) ← 0
LD A,#3H
LD IPR,A
EI ;IPR.3 (IME) ← 1
EXTERNAL INTERRUPT 0 AND 1 MODE REGISTERS (IMOD0 and IMOD1)
The following components are used to process external interrupts at the INT0 and INT1 pins:
—Noise filtering circuit for INT0
—Edge detection circuit
—Two mode registers, IMOD0 and IMOD1
The mode registers are used to control the triggering edge of the input signal. IMOD0 and IMOD1 settings let you
choose either the rising or falling edge of the incoming signal as the interrupt request trigger. The INT4 interrupt
is an exception since its input signal generates an interrupt request on both rising and falling edges. Since INT2 is
a qusi-interrupt, the interrupt request flag (IRQ2) must be cleared by software.
FB4H IMOD0.3 "0" IMOD0.1 IMOD0.0
FB5H "0" "0" "0" IMOD1.0
FB6H"0" IMOD2.2 IMOD2.1 IMOD2.0
IMOD0, IMOD1 and IMOD2 are addressable by 4-bit write instructions. RESET clears all IMOD values to logic
zero, selecting rising edges as the trigger for incoming interrupt requests.
Table 7-5. IMOD0 and IMOD1 Register Organization
IMOD0 IMOD0.3 0IMOD0.1 IMOD0.0 Effect of IMOD0 Settings
0Select CPU clock for sampling
1Select fxx/64 sampling clock
0 0 Rising edge detection
0 1 Falling edge detection
1 0 Both rising and falling edge detection
1 1 IRQ0 flag cannot be set to "1"
IMOD1 000IMOD1.0 Effect of IMOD1 and IMOD2 Settings
0Rising edge detection
1Falling edge detection