I/O PORTS

KS57C2308/P2308/C2316/P2316

 

 

PORT 2 CIRCUIT DIAGRAM

VDD

 

TCLO0

 

PUMOD.2

CLO

 

 

 

 

BUZ

 

 

PM2

8

P2.0/TCLO0

 

 

P2.1

Output

 

 

1, 4

 

Latch

P2.2/CLO

 

 

 

P2.3/BUZ

 

 

 

M

 

 

U

1, 4

 

X

 

NOTE: When a port pin acts as an output, its pull-up resistor is automatically disabled, even though the port's pull-up resistor is enabled by bit settings to the pull-up resistor mode register (PUMOD).

Figure 10-3. Port 2 Circuit Diagram

10-8

Page 218
Image 218
Samsung KS57C2308 manual Port 2 Circuit Diagram