Vent Load EMB, ERB, and Vector Address, VENTn | Samsung KS57C2308

SAM47 INSTRUCTION SETKS57C2308/P2308/C2316/P2316

VENT — Load EMB, ERB, and Vector Address

VENTn	dst

Operation:	Operand	Operation Summary	Bytes	Cycles

	EMB (0,1)	Load enable memory bank flag (EMB) and the enable	2	2
	ERB (0,1)	register bank flag (ERB) and program counter to
	ADR	vector address, then branch to the corresponding
		location.

Description: The VENT instruction loads the contents of the enable memory bank flag (EMB) and enable register bank flag (ERB) into the respective vector addresses. It then points the interrupt service routine to the corresponding branching locations. The program counter is loaded automatically with the respective vector addresses which indicate the starting address of the respective vector interrupt service routines.

The EMB and ERB flags should be modified using VENT before the vector interrupts are acknowledged. Then, when an interrupt is generated, the EMB and ERB values of the previous routine are automatically pushed onto the stack and then popped back when the routine is completed.

After the return from interrupt (IRET) you do not need to set the EMB and ERB values again. Instead, use BITR and BITS to clear these values in your program routine.

The starting addresses for vector interrupts and reset operations are pointed to by the VENTn instruction. These starting addresses must be located in ROM ranges 0000H–3FFFH. Generally, the VENTn instructions are coded starting at location 0000H.

The format for VENT instructions is as follows:

VENTn

d1,d2,ADDR

EMB

← d1 ("0" or "1")

ERB

← d2 ("0" or "1")

PC ← ADDR (address to branch

n = device-specific module address code (n = 0–n)

Operand

Binary Code

Operation Notation

EMB (0,1)

E

E

a13

a12

a11

a10

a9

a8

ROM (2 x n) 7–6 ← EMB, ERB

ERB (0,1)

M

R

ROM (2 x n) 5–4 ← PC13–12

ADR

B

B

ROM (2 x n) 3–0 ← PC11–8

ROM (2 x n + 1) 7–0 ← PC7–0

(n = 0, 1, 2, 3, 4, 5, 6, 7)

a7

a6

a5

a4

a3

a2

a1

a0

5-88

Image 162

Samsung KS57C2308 manual Vent Load EMB, ERB, and Vector Address, VENTn

Contents

Product Overview Overview Bit Timer/Counter PinsBit Basic Timer Watch Timer Block Diagram KS57C2308 INT1 INT4INT0 INT2 Test signal input must be connected to V SS Test PIN Circuit Diagrams Pin Circuit Type E P4, P5 General-Purpose Program Memory Address SpacesOverview Vector Addresses EMB ERB GENERAL-PURPOSE Memory AreasVector Address Area PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 + Programming TIP Defining Vectored Interrupts + Programming TIP Using the REF Look-Up Table Instruction Reference Area Data Memory RAM Data Memory Addressing Modes Memory Banks 0, 1,F80H-FFFH Working Registers RMCL1 @HL,A Incs SMB + Programming TIP Clearing Data Memory Banks 0Ramclr SMB RMCL0 @HL,A Incs Working Registers Working Register Map Working Register Banks Paired Working Registers Special-Purpose Working Registers SRB + Programming TIP Selecting the Working Register AreaINT0 Push Incs WX,EA YZ,EA POP SP7 SP6 SP5 SP4 Stack Pointer SPSP3 SP2 SP1 + Programming TIP Initializing the Stack Pointer Call Instructions Push OperationsPush Instructions Interrupt Routines RET and Sret Instructions POP OperationsPOP Instructions Iret Instructions BSC Register Organization Name Address Bit Program Counter PC MSB LSB FB0H IS1 IS0 EMB ERB FB1H SC2 SC1 SC0 Interrupt Status Flag Bit Settings Interrupt Status Flags IS0, IS1IS1 IS0 + Programming TIP Using the EMB Flag to Select Memory Banks EMB Flag EMB ERB Flag ERB HL,EA Skip Condition Flags SC2, SC1, SC0 Carry Flag CValid Carry Flag Manipulation Instructions Operation Type HL,#0AAH ADC EA,HLBand Address Spaces Addressing Modes RAM Address Structure Reset Bitr EMB EMB and ERB Initialization Values+ Programming TIP Initializing the EMB and ERB Flags Enable Memory Bank Settings EMB =EMB-Independent Addressing Select Bank Register SB Select Memory Bank SMB Instruction Direct and Indirect Addressing BIT AddressingBank Mapping Bit Indirect Addressing Adata EQU @HL@WL Bdata EQU 8EH SMB Cpse @HL Bdata EQUHL,#BDATA WX,#ADATA Comp @WL Sret Decs Comp RET Xchd @HL Bit Indirect Addressing ExampleHL,#BDATA WX,#ADATA Trans @WL SMB HL,#BDATA WX,#ADATA Trans @WL BDATA,EA EA,P4SMB ADATA,EA Bdata EQU 8EH SMB EA,P4 HL,#ADATA EA,@HL SMB HL,#ADATA EA,@HL Memory MAP MAP for Hardware Registers I/O Map for Memory Bank Addressing Mode Register Bit Fbah INT B IEW Irqw FB7H ScmodFB8H INT a IE4 IRQ4 IEB Irqb Fbch INT C IET0 IRQT0 Register Descriptions Register Description Format Bmod Basic Timer Mode Register Read/Write Bit Addressing Basic Timer Restart BitBit Identifier Clmod Clock Output Mode Register FD0HClock Source and Frequency Selection Control Bits IE0, 1, IRQ0, 1 INT0, 1 Interrupt Enable/Request Flags FbehIE1 IRQ1 IE0 IRQ0 IE2, IRQ2 INT2 Interrupt Enable/Request Flags FbfhIE2 IRQ2 FB8H IE4, IRQ4 INT4 Interrupt Enable/Request FlagsIEB, Irqb Intb Interrupt Enable/Request Flags IE4 IRQ4 IEB Irqb Fbdh IES, Irqs Ints Interrupt Enable/Request FlagsInts Interrupt Enable Flag IES Irqs Fbch IET0, IRQT0 INTT0 Interrupt Enable/Request FlagsINTT0 Interrupt Enable Flag IET0 IRQT0 Fbah IEW, Irqw Intw Interrupt Enable/Request FlagsIntw Interrupt Enable Flag IEW Irqw IMOD0 External Interrupt 0 INT0 Mode Register External Interrupt Mode Control BitsFB4H IMOD1.0 IMOD1 External Interrupt 1 INT1 Mode RegisterFB5H External Interrupt 1 Edge Detection Control Bit IMOD2.2 IMOD2.1 IMOD2.0 IMOD2 External Interrupt 2 INT2 Mode RegisterFB6H External Interrupt 2 Edge Detection Selection Bit FB2H Interrupt Master Enable BitIPR Interrupt Priority Register IME F8EH LCD Clock Output Disable/Enable BitLcon LCD Output Control Register Read/Write Bit Addressing LCD Bias Selection Bit LCD Clock Lcdck Frequency Selection Bits Lmod LCD Mode RegisterF8DH, F8CH Duty and Bias Selection for LCD Display FB3H Pcon Power Control RegisterRead/Write Bit Addressing CPU Operating Mode Control Bits CPU Clock Frequency Selection Bits PMG1 Port I/O Mode Flags Group 1 Port 3 FE9H, FE8H PMG2 Port I/O Mode Flags Group 2 Port 2, 4, 5, FEDH, FechPM7 PM5 PM4 PM2 PNE N-Channel Open-Drain Mode Register FD7H, FD6H PSW Program Status Word FB1H, FB0HSC2-SC0 SC1 IS1 IS0 EMB ERB Pumod Pull-Up Resistor Mode Register FDDH, FdchPUR7 PUR6 PUR5 PUR4 PUR3 PUR2 PUR1 PUR0 Scmod System Clock Mode Control Register FB7H1Bit Smod Serial I/O Mode Register FE1H, FE0H Enable/Disable Timer/Counter 0 Bit TMOD0 Timer/Counter 0 Mode Register F91H, F90HTimer/Counter 0 Input Clock Selection Bits Clear Counter and Resume Counting Control Bit TOE0 TOE Timer Output Enable Flag RegisterTimer/Counter 0 Output Enable Flag Bit3 F9AH Wdflag Watchdog Timer Counter Clear Flag RegisterWatchdog Timer Counter Clear Flag Wdtcf Wdmod Wdmod Watchdog Timer Mode Register F99H, F98HWatchdog Timer Enable/Disable Control 5AH Wmod Watch Timer Mode Register F89H, F88H Instruction SET Features SAM47 Instruction SET Instruction Reference Area Reducing Instruction Redundancy Bitr EMB Flexible Bit Manipulation Instructions Which Have Skip ConditionsInstructions Which Affect the Carry Flag ADC and SBC Instruction Skip Conditions ADC A,@HLSBC A,@HL Symbols and Conventions Data Type Symbols Instruction Operand Notation Symbol DefinitionRegister Identifiers Full Register Name Opcode Definitions Indirect Register Opcode DefinitionsOpcode Definitions Direct Register @HL @WX @WL HIGH-LEVEL Summary Cpse IdleStop EA,RR Xchi @HL XCHEA,DA DA,A ADS COMADC @HL SBC @HL Btstz Bitr Binary Code Summary SCF RCF CCF First Byte Condition PC13-8 ← SP + 1 SP Ra,#im Ra ← im RR,#imm RR ← imm EA,RR EA ← EA and RR EA,RR EA ← EA or RREA,RR EA ← EA XOR RR ← a + HL + C Skip if C = Second Byte Bit Addresses FB0H-FBFH FF0H-FFFH LDB Instruction Descriptions Operation Operand Operation Summary Bytes Cycles ADC Add With CarryADC Operand Binary Code Operation Notation #8H ← 8H ADS EA,HL ADS Add And Skip On OverflowADS JPS YYY EA ← 0C3H + 12H = 0D5H Logical SMB Band Band Bit LogicalBand Band C,P1.@L Flag EQU Band @H+FLAG FF1H-FF9H Bitr Bit ResetBitr Bitr P2.0 BP2 Bitr Incs BP2 Bits Bit Set BitsBits P2.0 BP2 Bits BOR Bit Logical or BOR BOR @H+FLAG LABEL2 Btsf Bit Test and Skip on FalseBtsf LABEL3 BP2 Btsf RET Incs BP2 Btst Bit Test and Skip on True Btst BP2 Btst Btstz Bit Test and Skip on True Clear Bit BtstzBP2 Btstz Btstz @H+FLAG Bits @H+FLAG Bxor Bit Exclusive or BxorRCF Bxor C,P1.0 Bxor @H+FLAG Call Call Procedure Call OperationOperand Operation Summary Bytes Cycles Calls Play Calls Call Procedure ShortCalls Operation 0FFH 0FEH EMB, ERB 0FDH 0FCH 0FBH 0FAH CCF Complement Carry Flag CCF COM Complement Accumulator COMCOM a Cpse Compare and Skip if Equal CpseCpse EA,HL RET Decs HL Decs Decrement and Skip on BorrowDecs Call PLAY1 DI Disable Interrupts EI Enable Interrupts Idle Idle Operation IdleIdle NOP Incs Increment and Skip on Carry IncsIncs @HL IS1 IS0 EMB ERB Iret Return From InterruptIret SC2 SC1 SC0 ADR14 JP JumpJP Operation Jump to direct address 14 bits ADR12 JPS Jump ShortJPS Operation Jump direct in page 12 bits JR Jump Relative Very Short EA,WX ADS WX,EA JR KKJPS AAA BBB CCC DDD JPS YYY XXX LD LD Load Description Operand Binary Code Operation Notation Instruction Operation Description and Guidelines Examples Instruction Operation Description and Guidelines LDB Load Bit LDB Flag EQU 20H.3 RCF FlagLDB @H+FLAG LDB @H+FLAG,C Call Display JPS Main ORG LDC Load Code ByteLDC Display LDC Display LD ORG 01FDH01FFH LDC LDD Load Data Memory and Decrement LDD Operation LDI Load Data Memory and Increment LDI OperationHL,#2FH LDI @HL NOP No Operation NOPStop NOP Or Logical or Or EA,@HL POP Pop From Stack POPPOP HL Push Push Onto Stack PushPush HL RCF Reset Carry Flag RCF REF Reference Instruction OperationOperand Operation Summary Bytes Cycles Memc Reference code BBB EA,#FFH CCC Tcall SUB1 DDD TJP SUB2 BBB EA,#FFH CCC Call SUB1 DDD SUB2AAA LD Tcall SUB1 Opcode Symbol InstructionHL,#0FH TJP SUB2 ORG RET Return From Subroutine RETPSW ← EMB,ERB RRC Rotate Accumulator Right Through Carry RRCRRC a SCF SBC EA,HL SBC Subtract With CarrySBC RCF SBC EA,HL #8H RCF SBS EA,HL SBS SubtractSBS SCF SBS EA,HL SCF Set Carry Flag SCF Addresses Register Areas Bank SMB Select Memory BankSMB Format Binary Code Operation Notation ERB Setting SRB Settings Selected Register Bank SRB Select Register BankSRB Sret Return From Subroutine and Skip Sret Stop Stop Operation Stop Vent Load EMB, ERB, and Vector Address VENTn VENTn Example The instruction sequence XCH Exchange a or EA with Nibble or Byte XCHXCH EA,@HL Xchd Exchange and Decrement Xchd OperationYYY Xchd @HL HL,#2FH Xchi Exchange and IncrementXchi Operation YYY Xchi @HL XOR Logical Exclusive or XORXOR EA,HL SAM47 Instruction SET Oscillator Circuits Interrupts Power-Down Page Oscillator Circuits CPU Clock Notation Using a Subsystem Clock Clock Control Registers Clock Circuit Diagram STO Main System Oscillator Circuits Subsystem Oscillator Circuits PCON.1 PCON.0 Power Control Register PconPcon Bit Settings Resulting CPU Operating Mode SCMOD.0 = + Programming TIP Setting the CPU Clock PCON,AInstruction Cycle Times SCMOD.3 SCMOD.2 SCMOD.0 System Clock Mode Register ScmodFB7H SCMOD.3 SCMOD.2 SCMOD.0 Scmod Fx Oscillation Fxt Oscillation Oscillator CIRCUITSKS57C2308/P2308/C2316/P2316 KS57C2308/P2308/C2316/P2316OSCILLATOR Circuits Switching the CPU Clock Elapsed Machine Cycles During CPU Clock Switch CLMOD.1 CLMOD.0 Clock Output Mode Register ClmodResult of CLMOD.3 Setting Clock Source Frequency Clock Output Procedure Clock Output Circuit + Programming TIP CPU Clock Output to the CLO Pin PMG2,EACLMOD,A INT0, INT1, INT4 Interrupt Types and Corresponding Port Pins Interrupt NameInterrupts INTB, INTT0, Ints Software-Generated Interrupts Power-Down Mode ReleaseVectored Interrupts Multiple Interrupts Interrupt Execution Flowchart Interrupt Control Circuit Diagram Multiple Interrupts Two-Level Interrupt Handling Multi-Level Interrupt Handling Result of IPR Bit Setting Standard Interrupt Priorities Default PriorityInterrupt Priority Register Settings Interrupt Priority Register IPR IMOD0 IMOD0.3 IMOD0.1 IMOD0.0 IMOD1 IMOD1.0 INT1 IMOD0 External INTERRUPT0 and INTERRUPT1 Mode RegistersINT0 Noise Filter Edge Clock Selector IRQ0 IRQ1 Edge IMOD1 Effect of IMOD2 Settings External Interrupt 2 Mode Register IMOD2IMOD2 Register Bit Settings FB6H IMOD2.2 IMOD2.1 IMOD2.0 Circuit Diagram for INT2 and KS0-KS7 Pins Interrupt Flags IME IPR.2 IPR.1 IPR.0 Interrupt Request Flags IRQx + Programming TIP Enabling the Intb and INT4 Interrupts Intb Btstz IrqbIret INT4 Bitr IRQ4 POWER-DOWN Stop Idle CPU Idle Mode Timing Diagrams Timing When Idle Mode is Released by Reset Stop Mode Timing Diagrams Timing When Stop Mode is Released by Reset IMOD2,A Keyclk Call MA2SUBP2,EA SMB Bitr Irqw IRQ2 Bits IEW IE2 CLKS1 Call Watdis Port PIN Configuration for POWER-DOWN P3.0/LCDCK Recommended Connections for Unused PinsP3.1/LCDSY SEG0-SEG23 POWER-DOWN Timing for Oscillation Stabilization After Reset Data Memory RAM Hardware Register Values After ResetProgram Status Word PSW Clocks Watchdog Timer Basic TimerTimer/Counters 0 LCD Driver/Controller KS57C2308/P2308/C2316/P2316 Channel Open-Drain Mode Register PNE Port Mode FlagsPull-Up Resistor Mode Register Pumod 10 I/O Ports P6,EA Port Mode Flags PM Flags PULL-UP Resistor Mode Register PumodPumod ID LCD Output Segments Bit Output Pins Channel OPEN-DRAIN Mode Register PNELMOD.7 and LMOD.6 Setting for Port 8 Output Control PIN Addressing for Output Port 1FAH SEG26 SEG24SEG25 1FBH SEG27 Port 0 Circuit Diagram Port 0 Circuit Diagram Port 1 Circuit Diagram IMOD0 IMOD1 Port 2 Circuit Diagram Port 2 Circuit Diagram Port 3 and 6 Circuit Diagram Port 3 and 6 Circuit Diagram Port 4 and 5 Circuit Diagram Port 4 and 5 Circuit Diagram Port 7 Circuit Diagram Port 7 Circuit Diagram 10-12 KS57C2308/P2308/C2316/P2316 Timers and TIMER/COUNTERS Interval Timer Function Watchdog Timer FunctionOscillation Stabilization Interval Control RAM Basic Timer Register Overview Type Description SizeAddressing Reset Name Mode Wdtcf Basic Timer Input Clock Interval Time Basic Timer Mode Register BmodBasic Timer Mode Register Bmod Organization BMOD.3 Basic Timer Counter Bcnt Basic Timer Operation Sequence + Programming TIP Using the Basic Timer Watchdog Timer Counter Clear Flag Wdtcf Watchdog Timer Mode Register WdmodWatchdog Timer Counter Wdcnt Bmod + Programming TIP Using the Watchdog Timer Reset Bits EMB SMBBMOD,A Main Bits Wdtcf BIT TIMER/COUNTER 0 TC0 TC0 Function Summary TC0 Component Summary TC0 Circuit Diagram TC0 Register Overview Type Description Size TC0 ENABLE/DISABLE Procedure Enable Timer/CounterDisable Timer/Counter TC0 Programmable TIMER/COUNTER Function TC0 Operation Sequence TMOD0.5 TMOD0.4 TMOD0 Settings for TCL0 Edge DetectionTC0 Event Counter Function TCL0 Edge Detection TREF0,EA EA,#4CH TMOD0,EA + Programming TIP TC0 Signal Output to the TCLO0 PinTC0 Clock Frequency Output Bits TOE0 TC0 External Input Signal Divider TC0 Serial I/O Clock GenerationTREF0,EA EA,#0CH TMOD0,EA TC0 Mode Register TMOD0 Resulting Counter Source and Clock Frequency TMOD0.6, TMOD0.5, and TMOD0.4 Bit SettingsTMOD0.6 TMOD0.5 TMOD0.4 + Programming TIP Restarting TC0 Counting Operation TC0 Timing Diagram TC0 Counter Register TCNT0 MSB LSB TC0 Output Enable Flag TOE0TC0 Reference Register TREF0 TC0 Output Latch TOL0 + Programming TIP Setting a TC0 Timer Interval TREF0,EA Using a System or Subsystem Clock Source Real-Time and Watch-Time MeasurementClock Source Generation for LCD Controller Timing Tests in High-Speed Mode Check Subsystem Clock Level FeatureBuzzer Output Frequency Generator Watch Timer Circuit Diagram Watch Timer Mode Register Wmod + Programming TIP Using the Watch Timer WMOD,EA Bits IEWClock Btstz Irqw LCD CONTROLLER/DRIVER Data BUS LCD Controller Driver LCD Circuit Diagram LCD Circuit Diagram LCD RAM Address Area LCON.0 LMOD.3 COM0-COM3 SEG0-SEG31 LCON.0 and LMOD.3 Bit SettingsLCD Control Register Lcon P8.0-P8.7 LCD Mode Register Lmod LMOD.5 LMOD.4LMOD.3 LMOD.2 LMOD.1 LMOD.0 GND LCD Power Supply Static Mode BiasLCD Drive Voltage LCD Voltage Dividing Resistors Voltage Dividing Resistor Circuit Diagrams Common COM Signals LCD Common Signal Waveform Static LCD Common Signal Waveform at 1/2 Bias 1/2, 1/3 Duty LCD Common Signal Waveform at 1/3 Bias 1/3, 1/4 Duty SEG Segment SEG SignalsSelect/No-Select Signals for LCD Static Display Mode Select No-select Select/No-Select Signals for LCD 1/2 Bias Display Mode Select Non-select Select/No-Select Signals for LCD 1/3 Bias Display Mode 10. Select/No-select Bias Signals in 1/3 Bias Display Mode 11. LCD Signal Waveforms in Static Mode COM0 SEG11 SEG12 VLC0 VSS +VLCD 0 Vlcd 12. LCD Connection Example in Static Mode 13. LCD Signal Waveforms at 1/2 Duty, 1/2 Bias COM0 COM1 SEG9 14. LCD Connection Example at 1/2 Duty, 1/2 Bias 15. LCD Signal Waveforms at 1/3 Duty, 1/2 Bias COM0 COM1 COM2 SEG12 16. LCD Connection Example at 1/3 Duty, 1/2 Bias 17. LCD Signal Waveforms at 1/3 Duty, 1/3 Bias 18. LCD Connection Example at 1/3 Duty, 1/3 Bias 19. LCD Signal Waveforms at 1/4 Duty, 1/3 Bias COM0 COM1 COM2 COM3 SEG13 20. LCD Connection Example at 1/4 Duty, 1/3 Bias 12-24 Serial I/O Interface Serial I/O Operation Sequence Serial I/O Interface Circuit Diagram SMOD.1 Serial I/O Mode Register SmodSMOD.0 SMOD.2 Serial I/O Timing Diagrams SIO Timing in Transmit/Receive Mode Bitr EMB EA,TDATA Serial I/O Buffer Register SbufSBUF,EA EA,#0EEH SMOD,EA SBUF,EA EA,#4FH SMOD,EA XCH EA,SBUF SBUF,EA EA,#8FH SMOD,EABits IES Ints Push Bits SMOD.3 SBUF,EA EA,#0FH SMOD,EA High Speed SIO Transmission 13-8 Electrical Data Standard Electrical CharacteristicsStop Mode Characteristics and Timing Waveforms Miscellaneous Timing Waveforms Parameter Symbol Conditions Min Typ Max Units Parameter Symbol Conditions Rating UnitsD.C. Electrical Characteristics Absolute Maximum Ratings Output low D.C. Electrical Characteristics Concluded Stop mode DD = 5 V ± 10% CPU = fx/4, Scmod = 0100B Main System Clock Oscillator Characteristics Subsystem Clock Oscillator Characteristics Parameter Symbol Condition Min Typ Max UnitsInput/Output Capacitance A.C. Electrical Characteristics Input Width Parameter Symbol Conditions Min Typ Max Unit Released by Reset 17/fx Time Released by interrupt Timing Waveforms A.C. Timing Measurement Points Except for XIN and Xtin TCL0 Timing 10. Serial Data Transfer Timing QFP-1420C Package Dimensions Mechanical Data 15-2 16 KS57P2308/P2316 OTP KS57P2308/KS57P2316 Operating Mode Characteristics REGTest 16-4 16-5 KS57P2308/P2316 OTPKS57C2308/P2308/C2316/P2316 16-7 16-8 16-9 16-10 Timing Waveforms 16-12 16-13 11. Serial Data Transfer Timing 12. OTP Programming Algorithm KS57P2308/P2316 OTP KS57C2308/P2308/C2316/P2316 16-16 SASM57 ShineSama Assembler HEX2ROM Smds Product Configuration SMDS2+ 17-2 TB572308A/16A Target Board Xtal MDS SMDS2/SMDS2+ XTI Idle LEDStop LED Pin Connectors for TB572308A/16A DIP KS57 Series Mask ROM Order Form Page Customer Risk Order Agreement KS57 Series Request for Production AT Customer RiskRisk Order Information Order Quantity and Delivery SchedulePage Prom KS57C2308 Mask Option Selection FormAttachment Check one Customer Checksum Company Name Signature EngineerPage KS57C2316 Mask Option Selection Form + What is the purpose of this order? KS57 Series OTP Factory Writing Order Form 1/2Page + Are you going to continue ordering this device? KS57P2308 OTP Factory Writing Order Form 2/2Device Number If so, how much will you be ordering? PCSPage KS57P2316 OTP Factory Writing Order Form 2/2