TIMERS and TIMER/COUNTERS KS57C2308/P2308/C2316/P2316
11-4
BASIC TIMER MODE REGISTER (BMOD)
The basic timer mode register, BMOD, is a 4-bit write-only register. Bit 3, the basic timer start control bit, is also
1-bit addressable. All BMOD values are set to logic zero following RESET and interrupt request signal generation
is set to the longest interval. (BT counter operation cannot be stopped.) BMOD settings have the following
effects:
—Restart the basic timer;
—Control the frequency of clock signal input to the basic timer;
—Determine time interval required for clock oscillation to stabilize following the release of stop mode by an
interrupt.
By loading different values into the BMOD register, you can dynamically modify the basic timer clock frequency
during program execution. Four BT frequencies, ranging from fxx/212 to fxx/25, are selectable. Since BMOD's
reset value is logic zero, the default clock frequency setting is fxx/212.
The most significant bit of the BMOD register, BMOD.3, is used to restart the basic timer. When BMOD.3 is set
to logic one (enabled) by a 1-bit write instruction, the contents of the BT counter register (BCNT) and the BT
interrupt request flag (IRQB) are both cleared to logic zero, and timer operation is restarted.
The combination of bit settings in the remaining three registers — BMOD.2, BMOD.1, and BMOD.0 —
determines the clock input frequency and oscillation stabilization interval.
Table 11-2. Basic Timer Mode Register (BMOD) Organization
BMOD.3 Basic Timer Restart Bit
1Restart basic timer; clear IRQB, BCNT, and BMOD.3 to "0"
BMOD.2 BMOD.1 BMOD.0 Basic Timer Input Clock Interval Time
000 fxx/212 (1.02 kHz) 220/fxx (250 ms)
011 fxx/29 (8.18 kHz) 217/fxx (31.3 ms)
101 fxx/27 (32.7 kHz) 215/fxx (7.82 ms)
111 fxx/25 (131 kHz) 213/fxx (1.95 ms)
NOTES:
1. Clock frequencies and stabilization intervals assume a system oscillator clock frequency (fxx) of 4.19 MHz.
2. fxx = selected system clock frequency.
3. Oscillation stabilization time is the time required to stabilize clock signal oscillation after stop mode is released. The
data in the table column “Oscillation Stabilization” can also be interpreted as "Interrupt Interval Time."
4. The standard stabilization time for system clock oscillation following a RESET is 31.3 ms at 4.19 MHz.