REF Reference Instruction, Operation | Samsung KS57C2308 guide

KS57C2308/P2308/C2316/P2316	SAM47 INSTRUCTION SET

REF — Reference Instruction

REF

Operation:

dst

Operand		Operation Summary	Bytes	Cycles

memc	Reference code		1	1 (note)

NOTE: The instruction referenced by REF determines the instruction cycles.

Description: The REF instruction is used to rewrite into 1-byte form, arbitrary 2-byte or 3-byte instructions (or two 1-byte instructions) stored in the REF instruction reference area in program memory. REF reduces the number of program memory accesses for a program.

Operand			Binary Code						Operation Notation

memc	t7	t6	t5	t4	t3	t2	t1	t0	PC13–0 ← memc.5–0 + (memc +
									1).7–0

TJP and TCALL are 2-byte pseudo-instructions that are used only to specify the reference area:

1.When the reference area is specified by the TJP instruction, memc.7–6 = 00

PC13–0 ← memc.5–0 + (memc + 1).7–0

2.When the reference area is specified by the TCALL instruction, memc.7–6 = 01

(SP–4) (SP–1) (SP–2) ← PC12–0 SP–3 ← EMB, ERB, PC13–12 PC13–0 ← memc.5–0 + (memc + 1).7–0 SP ← SP–4

When the reference area is specified by any other instruction, the “memc” and “memc + 1” instructions are executed.

Instructions referenced by REF occupy 2 bytes of memory space (for two 1-byte instructions or one 2-byte instruction) and must be written as an even number from 0020H to 007FH in ROM. In addition, the destination address of the TJP and TCALL instructions must be located with the 3FFFH address. TJP and TCALL are reference instructions for JP/JPS and CALL/CALLS.

If the instruction following a REF is subject to the “redundancy effect”, the redundant instruction is skipped. If, however, the REF follows a redundant instruction, it is executed.

On the other hand, the binary code of a REF instruction is 1 byte. The upper 4 bits become the higher address bits of the referenced instruction, and the lower 4 bits of the referenced instruction becomes the lower address, producing a total of 8 bits or 1 byte (see Example 3 below).

NOTE

If the MSB value of the first one-byte binary code in instruction is “0”, the instruction cannot be referenced by a REF instruction.

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Samsung KS57C2308 manual REF Reference Instruction, Operand Operation Summary Bytes Cycles Memc Reference code

Contents

Overview Product Overview Bit Basic Timer PinsBit Timer/Counter Watch Timer Block Diagram KS57C2308 INT0 INT4INT1 INT2 Test Test signal input must be connected to V SS PIN Circuit Diagrams Pin Circuit Type E P4, P5 Overview Address SpacesGeneral-Purpose Program Memory Vector Addresses Vector Address Area GENERAL-PURPOSE Memory AreasEMB ERB PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 + Programming TIP Defining Vectored Interrupts Instruction Reference Area + Programming TIP Using the REF Look-Up Table Data Memory RAM F80H-FFFH Memory Banks 0, 1,Data Memory Addressing Modes Working Registers Ramclr SMB + Programming TIP Clearing Data Memory Banks 0RMCL1 @HL,A Incs SMB RMCL0 @HL,A Incs Working Register Map Working Registers Paired Working Registers Working Register Banks Special-Purpose Working Registers INT0 Push + Programming TIP Selecting the Working Register AreaSRB Incs WX,EA YZ,EA POP SP3 SP2 SP1 Stack Pointer SPSP7 SP6 SP5 SP4 + Programming TIP Initializing the Stack Pointer Push Instructions Push OperationsCall Instructions Interrupt Routines POP Instructions POP OperationsRET and Sret Instructions Iret Instructions BSC Register Organization Name Address Bit MSB LSB FB0H IS1 IS0 EMB ERB FB1H SC2 SC1 SC0 Program Counter PC IS1 IS0 Interrupt Status Flag Bit SettingsInterrupt Status Flags IS0, IS1 EMB Flag EMB + Programming TIP Using the EMB Flag to Select Memory Banks HL,EA ERB Flag ERB Valid Carry Flag Manipulation Instructions Operation Type Skip Condition Flags SC2, SC1, SC0Carry Flag C Band HL,#0AAHADC EA,HL Address Spaces Addressing Modes RAM Address Structure + Programming TIP Initializing the EMB and ERB Flags Reset Bitr EMBEMB and ERB Initialization Values EMB-Independent Addressing Enable Memory Bank SettingsEMB = Select Memory Bank SMB Instruction Select Bank Register SB Bank Mapping Direct and Indirect AddressingBIT Addressing Bit Indirect Addressing @WL @HLAdata EQU Bdata EQU 8EH SMB HL,#BDATA WX,#ADATA Comp @WL Bdata EQUCpse @HL Sret Decs Comp RET HL,#BDATA WX,#ADATA Trans @WL Bit Indirect Addressing ExampleXchd @HL SMB HL,#BDATA WX,#ADATA Trans @WL SMB ADATA,EA EA,P4BDATA,EA Bdata EQU 8EH SMB EA,P4 SMB HL,#ADATA EA,@HL HL,#ADATA EA,@HL MAP for Hardware Registers Memory MAP I/O Map for Memory Bank Addressing Mode Register Bit FB8H INT a IE4 IRQ4 IEB Irqb FB7H ScmodFbah INT B IEW Irqw Fbch INT C IET0 IRQT0 Register Descriptions Register Description Format Bit Identifier Bmod Basic Timer Mode RegisterRead/Write Bit Addressing Basic Timer Restart Bit Clock Source and Frequency Selection Control Bits Clmod Clock Output Mode RegisterFD0H IE1 IRQ1 IE0 IRQ0 IE0, 1, IRQ0, 1 INT0, 1 Interrupt Enable/Request FlagsFbeh IE2 IRQ2 IE2, IRQ2 INT2 Interrupt Enable/Request FlagsFbfh IEB, Irqb Intb Interrupt Enable/Request Flags IE4, IRQ4 INT4 Interrupt Enable/Request FlagsFB8H IE4 IRQ4 IEB Irqb Ints Interrupt Enable Flag IES, Irqs Ints Interrupt Enable/Request FlagsFbdh IES Irqs INTT0 Interrupt Enable Flag IET0, IRQT0 INTT0 Interrupt Enable/Request FlagsFbch IET0 IRQT0 Intw Interrupt Enable Flag IEW, Irqw Intw Interrupt Enable/Request FlagsFbah IEW Irqw FB4H IMOD0 External Interrupt 0 INT0 Mode RegisterExternal Interrupt Mode Control Bits FB5H IMOD1 External Interrupt 1 INT1 Mode RegisterIMOD1.0 External Interrupt 1 Edge Detection Control Bit FB6H IMOD2 External Interrupt 2 INT2 Mode RegisterIMOD2.2 IMOD2.1 IMOD2.0 External Interrupt 2 Edge Detection Selection Bit IPR Interrupt Priority Register Interrupt Master Enable BitFB2H IME Lcon LCD Output Control Register LCD Clock Output Disable/Enable BitF8EH Read/Write Bit Addressing LCD Bias Selection Bit F8DH, F8CH Lmod LCD Mode RegisterLCD Clock Lcdck Frequency Selection Bits Duty and Bias Selection for LCD Display Read/Write Bit Addressing CPU Operating Mode Control Bits Pcon Power Control RegisterFB3H CPU Clock Frequency Selection Bits FE9H, FE8H PMG1 Port I/O Mode Flags Group 1 Port 3 PM7 PM5 PM4 PM2 PMG2 Port I/O Mode Flags Group 2 Port 2, 4, 5,FEDH, Fech FD7H, FD6H PNE N-Channel Open-Drain Mode Register SC2-SC0 SC1 IS1 IS0 EMB ERB PSW Program Status WordFB1H, FB0H PUR7 PUR6 PUR5 PUR4 PUR3 PUR2 PUR1 PUR0 Pumod Pull-Up Resistor Mode RegisterFDDH, Fdch 1Bit Scmod System Clock Mode Control RegisterFB7H FE1H, FE0H Smod Serial I/O Mode Register Timer/Counter 0 Input Clock Selection Bits TMOD0 Timer/Counter 0 Mode Register F91H, F90HEnable/Disable Timer/Counter 0 Bit Clear Counter and Resume Counting Control Bit Timer/Counter 0 Output Enable Flag TOE Timer Output Enable Flag RegisterTOE0 Bit3 Watchdog Timer Counter Clear Flag Wdflag Watchdog Timer Counter Clear Flag RegisterF9AH Wdtcf Watchdog Timer Enable/Disable Control Wdmod Watchdog Timer Mode Register F99H, F98HWdmod 5AH Wmod Watch Timer Mode Register F89H, F88H SAM47 Instruction SET Instruction SET Features Instruction Reference Area Bitr EMB Reducing Instruction Redundancy Instructions Which Affect the Carry Flag Flexible Bit ManipulationInstructions Which Have Skip Conditions SBC A,@HL ADC and SBC Instruction Skip ConditionsADC A,@HL Register Identifiers Full Register Name Symbols and Conventions Data Type SymbolsInstruction Operand Notation Symbol Definition Opcode Definitions Direct Register Opcode DefinitionsOpcode Definitions Indirect Register @HL @WX @WL HIGH-LEVEL Summary Stop IdleCpse EA,RR EA,DA XCHXchi @HL DA,A ADC @HL COMADS SBC @HL Bitr Btstz Binary Code Summary SCF RCF CCF First Byte Condition PC13-8 ← SP + 1 SP Ra,#im Ra ← im RR,#imm RR ← imm EA,RR EA ← EA XOR RR EA,RR EA ← EA and RREA,RR EA ← EA or RR ← a + HL + C Skip if C = FB0H-FBFH FF0H-FFFH Second Byte Bit Addresses LDB Instruction Descriptions ADC ADC Add With CarryOperation Operand Operation Summary Bytes Cycles Operand Binary Code Operation Notation #8H ← 8H ADS ADS Add And Skip On OverflowADS EA,HL JPS YYY EA ← 0C3H + 12H = 0D5H Logical Band Band Bit LogicalSMB Band Band C,P1.@L Band @H+FLAG Flag EQU Bitr Bitr Bit ResetFF1H-FF9H Bitr P2.0 Incs BP2 BP2 Bitr Bits P2.0 Bits Bit SetBits BP2 Bits BOR BOR Bit Logical or BOR @H+FLAG Btsf Btsf Bit Test and Skip on FalseLABEL2 LABEL3 RET Incs BP2 BP2 Btsf Btst Btst Bit Test and Skip on True BP2 Btst BP2 Btstz Btstz Bit Test and Skip on True Clear BitBtstz Bits @H+FLAG Btstz @H+FLAG RCF Bxor C,P1.0 Bxor Bit Exclusive orBxor Bxor @H+FLAG Operand Operation Summary Bytes Cycles Call Call ProcedureCall Operation Calls Operation Calls Call Procedure ShortCalls Play 0FFH 0FEH EMB, ERB 0FDH 0FCH 0FBH 0FAH CCF CCF Complement Carry Flag COM a COM Complement AccumulatorCOM Cpse EA,HL RET Cpse Compare and Skip if EqualCpse Decs Decs Decrement and Skip on BorrowDecs HL Call PLAY1 DI Disable Interrupts EI Enable Interrupts Idle NOP Idle Idle OperationIdle Incs @HL Incs Increment and Skip on CarryIncs Iret Iret Return From InterruptIS1 IS0 EMB ERB SC2 SC1 SC0 JP Operation JP JumpADR14 Jump to direct address 14 bits JPS Operation JPS Jump ShortADR12 Jump direct in page 12 bits JR Jump Relative Very Short JPS AAA BBB CCC DDD JR KKEA,WX ADS WX,EA JPS YYY XXX LD LD Load Description Operand Binary Code Operation Notation Instruction Operation Description and Guidelines Examples Instruction Operation Description and Guidelines LDB LDB Load Bit LDB @H+FLAG FlagFlag EQU 20H.3 RCF LDB @H+FLAG,C LDC LDC Load Code ByteCall Display JPS Main ORG Display LDC 01FFH LDC Display LDORG 01FDH LDD Operation LDD Load Data Memory and Decrement HL,#2FH LDI @HL LDI Load Data Memory and IncrementLDI Operation Stop NOP NOP No OperationNOP Or EA,@HL Or Logical or POP HL POP Pop From StackPOP Push HL Push Push Onto StackPush RCF RCF Reset Carry Flag Operand Operation Summary Bytes Cycles Memc Reference code REF Reference InstructionOperation AAA LD BBB EA,#FFH CCC Tcall SUB1 DDD TJP SUB2BBB EA,#FFH CCC Call SUB1 DDD SUB2 HL,#0FH Opcode Symbol InstructionTcall SUB1 TJP SUB2 ORG PSW ← EMB,ERB RET Return From SubroutineRET RRC a RRC Rotate Accumulator Right Through CarryRRC SBC SBC Subtract With CarrySCF SBC EA,HL RCF SBC EA,HL #8H SBS SBS SubtractRCF SBS EA,HL SCF SBS EA,HL SCF SCF Set Carry Flag SMB SMB Select Memory BankAddresses Register Areas Bank Format Binary Code Operation Notation SRB ERB Setting SRB Settings Selected Register BankSRB Select Register Bank Sret Sret Return From Subroutine and Skip Stop Stop Stop Operation VENTn Vent Load EMB, ERB, and Vector Address VENTn Example The instruction sequence XCH EA,@HL XCH Exchange a or EA with Nibble or ByteXCH YYY Xchd @HL Xchd Exchange and DecrementXchd Operation Xchi Operation Xchi Exchange and IncrementHL,#2FH YYY Xchi @HL XOR EA,HL XOR Logical Exclusive orXOR SAM47 Instruction SET Oscillator Circuits Interrupts Power-Down Page CPU Clock Notation Oscillator Circuits Clock Control Registers Using a Subsystem Clock STO Clock Circuit Diagram Subsystem Oscillator Circuits Main System Oscillator Circuits Pcon Bit Settings Resulting CPU Operating Mode Power Control Register PconPCON.1 PCON.0 SCMOD.0 = Instruction Cycle Times + Programming TIP Setting the CPU ClockPCON,A FB7H SCMOD.3 SCMOD.2 SCMOD.0 Scmod System Clock Mode Register ScmodSCMOD.3 SCMOD.2 SCMOD.0 Fx Oscillation Fxt Oscillation Oscillator CIRCUITSKS57C2308/P2308/C2316/P2316 KS57C2308/P2308/C2316/P2316OSCILLATOR Circuits Switching the CPU Clock Elapsed Machine Cycles During CPU Clock Switch Result of CLMOD.3 Setting Clock Output Mode Register ClmodCLMOD.1 CLMOD.0 Clock Source Frequency Clock Output Circuit Clock Output Procedure CLMOD,A + Programming TIP CPU Clock Output to the CLO PinPMG2,EA Interrupts Interrupt Types and Corresponding Port Pins Interrupt NameINT0, INT1, INT4 INTB, INTT0, Ints Vectored Interrupts Power-Down Mode ReleaseSoftware-Generated Interrupts Multiple Interrupts Interrupt Execution Flowchart Interrupt Control Circuit Diagram Two-Level Interrupt Handling Multiple Interrupts Multi-Level Interrupt Handling Interrupt Priority Register Settings Standard Interrupt Priorities Default PriorityResult of IPR Bit Setting Interrupt Priority Register IPR IMOD1 IMOD1.0 IMOD0 IMOD0.3 IMOD0.1 IMOD0.0 INT0 Noise Filter Edge Clock Selector External INTERRUPT0 and INTERRUPT1 Mode RegistersINT1 IMOD0 IRQ0 IRQ1 Edge IMOD1 IMOD2 Register Bit Settings External Interrupt 2 Mode Register IMOD2Effect of IMOD2 Settings FB6H IMOD2.2 IMOD2.1 IMOD2.0 Circuit Diagram for INT2 and KS0-KS7 Pins IME IPR.2 IPR.1 IPR.0 Interrupt Flags Interrupt Request Flags IRQx Iret INT4 Bitr IRQ4 + Programming TIP Enabling the Intb and INT4 InterruptsIntb Btstz Irqb POWER-DOWN CPU Stop Idle Timing When Idle Mode is Released by Reset Idle Mode Timing Diagrams Timing When Stop Mode is Released by Reset Stop Mode Timing Diagrams P2,EA Keyclk Call MA2SUBIMOD2,A SMB Bitr Irqw IRQ2 Bits IEW IE2 CLKS1 Call Watdis Port PIN Configuration for POWER-DOWN P3.1/LCDSY Recommended Connections for Unused PinsP3.0/LCDCK SEG0-SEG23 POWER-DOWN Timing for Oscillation Stabilization After Reset Program Status Word PSW Hardware Register Values After ResetData Memory RAM Clocks Timer/Counters 0 Basic TimerWatchdog Timer LCD Driver/Controller KS57C2308/P2308/C2316/P2316 Pull-Up Resistor Mode Register Pumod Port Mode FlagsChannel Open-Drain Mode Register PNE 10 I/O Ports P6,EA Pumod ID Port Mode Flags PM FlagsPULL-UP Resistor Mode Register Pumod LMOD.7 and LMOD.6 Setting for Port 8 Output Control Channel OPEN-DRAIN Mode Register PNELCD Output Segments Bit Output Pins PIN Addressing for Output Port SEG25 SEG241FAH SEG26 1FBH SEG27 Port 0 Circuit Diagram Port 0 Circuit Diagram IMOD0 IMOD1 Port 1 Circuit Diagram Port 2 Circuit Diagram Port 2 Circuit Diagram Port 3 and 6 Circuit Diagram Port 3 and 6 Circuit Diagram Port 4 and 5 Circuit Diagram Port 4 and 5 Circuit Diagram Port 7 Circuit Diagram Port 7 Circuit Diagram 10-12 KS57C2308/P2308/C2316/P2316 Timers and TIMER/COUNTERS Oscillation Stabilization Interval Control Interval Timer FunctionWatchdog Timer Function Addressing Reset Name Mode Basic Timer Register Overview Type Description SizeRAM Wdtcf Basic Timer Mode Register Bmod Organization Basic Timer Mode Register BmodBasic Timer Input Clock Interval Time BMOD.3 Basic Timer Operation Sequence Basic Timer Counter Bcnt + Programming TIP Using the Basic Timer Watchdog Timer Counter Wdcnt Watchdog Timer Mode Register WdmodWatchdog Timer Counter Clear Flag Wdtcf Bmod BMOD,A Main Bits Wdtcf + Programming TIP Using the Watchdog TimerReset Bits EMB SMB TC0 Function Summary BIT TIMER/COUNTER 0 TC0 TC0 Component Summary TC0 Register Overview Type Description Size TC0 Circuit Diagram Disable Timer/Counter TC0 ENABLE/DISABLE ProcedureEnable Timer/Counter TC0 Operation Sequence TC0 Programmable TIMER/COUNTER Function TC0 Event Counter Function TMOD0 Settings for TCL0 Edge DetectionTMOD0.5 TMOD0.4 TCL0 Edge Detection TC0 Clock Frequency Output + Programming TIP TC0 Signal Output to the TCLO0 PinTREF0,EA EA,#4CH TMOD0,EA Bits TOE0 TREF0,EA EA,#0CH TMOD0,EA TC0 External Input Signal DividerTC0 Serial I/O Clock Generation TC0 Mode Register TMOD0 TMOD0.6 TMOD0.5 TMOD0.4 TMOD0.6, TMOD0.5, and TMOD0.4 Bit SettingsResulting Counter Source and Clock Frequency + Programming TIP Restarting TC0 Counting Operation TC0 Counter Register TCNT0 TC0 Timing Diagram TC0 Reference Register TREF0 TC0 Output Enable Flag TOE0MSB LSB TC0 Output Latch TOL0 TREF0,EA + Programming TIP Setting a TC0 Timer Interval Clock Source Generation for LCD Controller Using a System or Subsystem Clock SourceReal-Time and Watch-Time Measurement Buzzer Output Frequency Generator Timing Tests in High-Speed ModeCheck Subsystem Clock Level Feature Watch Timer Circuit Diagram Watch Timer Mode Register Wmod Clock Btstz Irqw + Programming TIP Using the Watch TimerWMOD,EA Bits IEW Data BUS LCD Controller Driver LCD CONTROLLER/DRIVER LCD Circuit Diagram LCD Circuit Diagram LCD RAM Address Area LCD Control Register Lcon LCON.0 and LMOD.3 Bit SettingsLCON.0 LMOD.3 COM0-COM3 SEG0-SEG31 P8.0-P8.7 LMOD.3 LMOD.2 LMOD.1 LMOD.0 LCD Mode Register LmodLMOD.5 LMOD.4 LCD Drive Voltage LCD Power Supply Static Mode BiasGND LCD Voltage Dividing Resistors Voltage Dividing Resistor Circuit Diagrams LCD Common Signal Waveform Static Common COM Signals LCD Common Signal Waveform at 1/2 Bias 1/2, 1/3 Duty LCD Common Signal Waveform at 1/3 Bias 1/3, 1/4 Duty Select/No-Select Signals for LCD Static Display Mode Segment SEG SignalsSEG Select No-select Select Non-select Select/No-Select Signals for LCD 1/2 Bias Display Mode 10. Select/No-select Bias Signals in 1/3 Bias Display Mode Select/No-Select Signals for LCD 1/3 Bias Display Mode COM0 SEG11 SEG12 VLC0 VSS +VLCD 0 Vlcd 11. LCD Signal Waveforms in Static Mode 12. LCD Connection Example in Static Mode COM0 COM1 SEG9 13. LCD Signal Waveforms at 1/2 Duty, 1/2 Bias 14. LCD Connection Example at 1/2 Duty, 1/2 Bias COM0 COM1 COM2 SEG12 15. LCD Signal Waveforms at 1/3 Duty, 1/2 Bias 16. LCD Connection Example at 1/3 Duty, 1/2 Bias 17. LCD Signal Waveforms at 1/3 Duty, 1/3 Bias 18. LCD Connection Example at 1/3 Duty, 1/3 Bias COM0 COM1 COM2 COM3 SEG13 19. LCD Signal Waveforms at 1/4 Duty, 1/3 Bias 20. LCD Connection Example at 1/4 Duty, 1/3 Bias 12-24 Serial I/O Operation Sequence Serial I/O Interface Serial I/O Interface Circuit Diagram SMOD.0 Serial I/O Mode Register SmodSMOD.1 SMOD.2 SIO Timing in Transmit/Receive Mode Serial I/O Timing Diagrams SBUF,EA EA,#0EEH SMOD,EA Serial I/O Buffer Register SbufBitr EMB EA,TDATA SBUF,EA EA,#4FH SMOD,EA Bits IES Ints Push SBUF,EA EA,#8FH SMOD,EAXCH EA,SBUF Bits SMOD.3 High Speed SIO Transmission SBUF,EA EA,#0FH SMOD,EA 13-8 Stop Mode Characteristics and Timing Waveforms Standard Electrical CharacteristicsElectrical Data Miscellaneous Timing Waveforms D.C. Electrical Characteristics Parameter Symbol Conditions Rating UnitsParameter Symbol Conditions Min Typ Max Units Absolute Maximum Ratings Output low Stop mode DD = 5 V ± 10% CPU = fx/4, Scmod = 0100B D.C. Electrical Characteristics Concluded Main System Clock Oscillator Characteristics Input/Output Capacitance Subsystem Clock Oscillator CharacteristicsParameter Symbol Condition Min Typ Max Units Input Width A.C. Electrical Characteristics Released by Reset 17/fx Time Released by interrupt Parameter Symbol Conditions Min Typ Max Unit Timing Waveforms A.C. Timing Measurement Points Except for XIN and Xtin TCL0 Timing 10. Serial Data Transfer Timing Mechanical Data QFP-1420C Package Dimensions 15-2 16 KS57P2308/P2316 OTP KS57P2308/KS57P2316 Test Operating Mode CharacteristicsREG 16-4 16-5 KS57P2308/P2316 OTPKS57C2308/P2308/C2316/P2316 16-7 16-8 16-9 16-10 Timing Waveforms 16-12 16-13 11. Serial Data Transfer Timing 12. OTP Programming Algorithm KS57P2308/P2316 OTP KS57C2308/P2308/C2316/P2316 16-16 Sama Assembler ShineSASM57 HEX2ROM Smds Product Configuration SMDS2+ 17-2 TB572308A/16A Target Board SMDS2/SMDS2+ Xtal MDS Stop LED XTIIdle LED DIP Pin Connectors for TB572308A/16A KS57 Series Mask ROM Order Form Page Risk Order Information KS57 Series Request for Production AT Customer RiskCustomer Risk Order Agreement Order Quantity and Delivery SchedulePage Attachment Check one KS57C2308 Mask Option Selection FormProm Customer Checksum Company Name Signature EngineerPage KS57C2316 Mask Option Selection Form KS57 Series OTP Factory Writing Order Form 1/2 + What is the purpose of this order?Page Device Number KS57P2308 OTP Factory Writing Order Form 2/2+ Are you going to continue ordering this device? If so, how much will you be ordering? PCSPage KS57P2316 OTP Factory Writing Order Form 2/2