Samsung KS57C2308 manual TC0 Serial I/O Clock Generation, TC0 External Input Signal Divider

TIMERS and TIMER/COUNTERS KS57C2308/P2308/C2316/P2316

TC0 SERIAL I/O CLOCK GENERATION

Timer/counter 0 can supply a clock signal to the clock selector circuit of the serial I/O interface for data shifter and clock counter operations. (These internal SIO operations are controlled in turn by the SIO mode register, SMOD). This clock generation function enables you to adjust data transmission rates across the serial interface.

Use TMOD0 and TREF0 register settings to select the frequency and interval of the TC0 clock signals to be used as SCK input to the serial interface. The generated clock signal is then sent directly to the serial I/O clock selector circuit (the TOE0 flag may be disabled).

TC0 EXTERNAL INPUT SIGNAL DIVIDER

By selecting an external clock source and loading a reference value into the TC0 reference register, TREF0, you can divide the incoming clock signal by the TREF0 value and then output this modified clock frequency to the TCLO0 pin. The sequence of operations used to divide external clock input can be summarized as follows:

1.Load a signal divider value to the TREF0 register.

2.Clear TMOD0.6 to "0" to enable external clock input at the TCL0 pin.

3.Set TMOD0.5 and TMOD0.4 to desired TCL0 signal edge detection.

4.Set port 2.0 mode flag (PM2) to output ("1").

5.Clear P2.0 output latch to "0".

6.Set TOE0 flag to "1" to enable output of the divided frequency to the TCLO0 pin

+PROGRAMMING TIP — External TCL0 Clock Output to the TCLO0 Pin

Output external TCL0 clock pulse to the TCLO0 pin (divided by four):

EXTERNAL (TCL0)

CLOCK PULSE

	TCLO0
	OUTPUT
	PULSE
BITS	EMB
SMB	15
LD	EA,#01H
LD	TREF0,EA
LD	EA,#0CH
LD	TMOD0,EA
LD	EA,#04H
LD	PMG2,EA	; P2.0 ← output mode
BITR	P2.0	; Clear P2.0 output latch
BITS	TOE0

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