MEMORY MAP KS57C2308/P2308/C2316/P2316
4-4
Table 4-1. I/O Map for Memory Bank 15 (Concluded)
Memory Bank 15 Addressing Mode
Address Register Bit 3 Bit 2 Bit 1 Bit 0 R/W 1-Bit 4-Bit 8-Bit
FF0H Port 0 .3 .2 .1 .0 RYes Yes No
FF1H Port 1 .3 .2 .1 .0 RYes Yes No
FF2H Port 2 .3 .2 .1 .0 R/W Yes Yes No
FF3H Port 3 .3 .2 .1 .0 R/W Yes Yes No
FF4H Port 4 .3 .2 .1 .0 R/W Yes Yes Yes
FF5H Port 5 .3/.7 .2/.6 .1/.5 .0/.4 R/W Yes Yes
FF6H Port 6 .3 .2 .1 .0 R/W Yes Yes Yes
FF7H Port 7 .3/.7 .2/.6 .1/.5 .0/.4 R/W Yes Yes
Locations, FF8H–FFFH, are not mapped.
NOTES:
1. Bit 3 in the WMOD register is read only.
2. “U” means that the value is unknown.
3.The carry flag can be read or written by specific bit manipulation instructions only.
REGISTER DESCRIPTIONS
In this section, register descriptions are presented in a consistent format to familiarize you with the
memory-mapped I/O locations in bank 15 of the RAM. Figure 4-1 describes the features of the register
description format. Register descriptions are arranged in alphabetical order. Programmers can use this section as
a quick-reference source when writing application programs.
Counter registers, buffer registers, and reference registers, as well as the stack pointer and port I/O latches, are
not included in these descriptions. More detailed information about how these registers are used is included in
Part II of this manual, "Hardware Descriptions”, in the context of the corresponding peripheral hardware module
descriptions.