Product Overview
Overview
Pins
Bit Basic Timer
Bit Timer/Counter
Watch Timer
Block Diagram
KS57C2308
INT4
INT0
INT1
INT2
Test signal input must be connected to V SS
Test
PIN Circuit Diagrams
Pin Circuit Type E P4, P5
Address Spaces
Overview
General-Purpose Program Memory
Vector Addresses
GENERAL-PURPOSE Memory Areas
Vector Address Area
EMB ERB
PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
+ Programming TIP Defining Vectored Interrupts
+ Programming TIP Using the REF Look-Up Table
Instruction Reference Area
Data Memory RAM
Memory Banks 0, 1,
F80H-FFFH
Data Memory Addressing Modes
Working Registers
+ Programming TIP Clearing Data Memory Banks 0
Ramclr SMB
RMCL1 @HL,A Incs SMB
RMCL0 @HL,A Incs
Working Registers
Working Register Map
Working Register Banks
Paired Working Registers
Special-Purpose Working Registers
+ Programming TIP Selecting the Working Register Area
INT0 Push
SRB
Incs WX,EA YZ,EA POP
Stack Pointer SP
SP3 SP2 SP1
SP7 SP6 SP5 SP4
+ Programming TIP Initializing the Stack Pointer
Push Operations
Push Instructions
Call Instructions
Interrupt Routines
POP Operations
POP Instructions
RET and Sret Instructions
Iret Instructions
BSC Register Organization Name Address Bit
Program Counter PC
MSB LSB FB0H IS1 IS0 EMB ERB FB1H SC2 SC1 SC0
IS1 IS0
Interrupt Status Flag Bit Settings
Interrupt Status Flags IS0, IS1
+ Programming TIP Using the EMB Flag to Select Memory Banks
EMB Flag EMB
ERB Flag ERB
HL,EA
Valid Carry Flag Manipulation Instructions Operation Type
Skip Condition Flags SC2, SC1, SC0
Carry Flag C
Band
HL,#0AAH
ADC EA,HL
Address Spaces
Addressing Modes
RAM Address Structure
+ Programming TIP Initializing the EMB and ERB Flags
Reset Bitr EMB
EMB and ERB Initialization Values
EMB-Independent Addressing
Enable Memory Bank Settings
EMB =
Select Bank Register SB
Select Memory Bank SMB Instruction
Bank Mapping
Direct and Indirect Addressing
BIT Addressing
Bit Indirect Addressing
@HL
@WL
Adata EQU
Bdata EQU 8EH SMB
Bdata EQU
HL,#BDATA WX,#ADATA Comp @WL
Cpse @HL
Sret Decs Comp RET
Bit Indirect Addressing Example
HL,#BDATA WX,#ADATA Trans @WL
Xchd @HL
SMB HL,#BDATA WX,#ADATA Trans @WL
EA,P4
SMB ADATA,EA
BDATA,EA
Bdata EQU 8EH SMB EA,P4
HL,#ADATA EA,@HL
SMB HL,#ADATA EA,@HL
Memory MAP
MAP for Hardware Registers
I/O Map for Memory Bank Addressing Mode Register Bit
FB7H Scmod
FB8H INT a IE4 IRQ4 IEB Irqb
Fbah INT B IEW Irqw
Fbch INT C IET0 IRQT0
Register Descriptions
Register Description Format
Bit Identifier
Bmod Basic Timer Mode Register
Read/Write Bit Addressing Basic Timer Restart Bit
Clock Source and Frequency Selection Control Bits
Clmod Clock Output Mode Register
FD0H
IE1 IRQ1 IE0 IRQ0
IE0, 1, IRQ0, 1 INT0, 1 Interrupt Enable/Request Flags
Fbeh
IE2 IRQ2
IE2, IRQ2 INT2 Interrupt Enable/Request Flags
Fbfh
IE4, IRQ4 INT4 Interrupt Enable/Request Flags
IEB, Irqb Intb Interrupt Enable/Request Flags
FB8H
IE4 IRQ4 IEB Irqb
IES, Irqs Ints Interrupt Enable/Request Flags
Ints Interrupt Enable Flag
Fbdh
IES Irqs
IET0, IRQT0 INTT0 Interrupt Enable/Request Flags
INTT0 Interrupt Enable Flag
Fbch
IET0 IRQT0
IEW, Irqw Intw Interrupt Enable/Request Flags
Intw Interrupt Enable Flag
Fbah
IEW Irqw
FB4H
IMOD0 External Interrupt 0 INT0 Mode Register
External Interrupt Mode Control Bits
IMOD1 External Interrupt 1 INT1 Mode Register
FB5H
IMOD1.0
External Interrupt 1 Edge Detection Control Bit
IMOD2 External Interrupt 2 INT2 Mode Register
FB6H
IMOD2.2 IMOD2.1 IMOD2.0
External Interrupt 2 Edge Detection Selection Bit
Interrupt Master Enable Bit
IPR Interrupt Priority Register
FB2H
IME
LCD Clock Output Disable/Enable Bit
Lcon LCD Output Control Register
F8EH
Read/Write Bit Addressing LCD Bias Selection Bit
Lmod LCD Mode Register
F8DH, F8CH
LCD Clock Lcdck Frequency Selection Bits
Duty and Bias Selection for LCD Display
Pcon Power Control Register
Read/Write Bit Addressing CPU Operating Mode Control Bits
FB3H
CPU Clock Frequency Selection Bits
PMG1 Port I/O Mode Flags Group 1 Port 3
FE9H, FE8H
PM7 PM5 PM4 PM2
PMG2 Port I/O Mode Flags Group 2 Port 2, 4, 5,
FEDH, Fech
PNE N-Channel Open-Drain Mode Register
FD7H, FD6H
SC2-SC0 SC1 IS1 IS0 EMB ERB
PSW Program Status Word
FB1H, FB0H
PUR7 PUR6 PUR5 PUR4 PUR3 PUR2 PUR1 PUR0
Pumod Pull-Up Resistor Mode Register
FDDH, Fdch
1Bit
Scmod System Clock Mode Control Register
FB7H
Smod Serial I/O Mode Register
FE1H, FE0H
TMOD0 Timer/Counter 0 Mode Register F91H, F90H
Timer/Counter 0 Input Clock Selection Bits
Enable/Disable Timer/Counter 0 Bit
Clear Counter and Resume Counting Control Bit
TOE Timer Output Enable Flag Register
Timer/Counter 0 Output Enable Flag
TOE0
Bit3
Wdflag Watchdog Timer Counter Clear Flag Register
Watchdog Timer Counter Clear Flag
F9AH
Wdtcf
Wdmod Watchdog Timer Mode Register F99H, F98H
Watchdog Timer Enable/Disable Control
Wdmod
5AH
Wmod Watch Timer Mode Register F89H, F88H
Instruction SET Features
SAM47 Instruction SET
Instruction Reference Area
Reducing Instruction Redundancy
Bitr EMB
Instructions Which Affect the Carry Flag
Flexible Bit Manipulation
Instructions Which Have Skip Conditions
SBC A,@HL
ADC and SBC Instruction Skip Conditions
ADC A,@HL
Register Identifiers Full Register Name
Symbols and Conventions Data Type Symbols
Instruction Operand Notation Symbol Definition
Opcode Definitions
Opcode Definitions Direct Register
Opcode Definitions Indirect Register
@HL @WX @WL
HIGH-LEVEL Summary
Idle
Stop
Cpse
EA,RR
XCH
EA,DA
Xchi @HL
DA,A
COM
ADC @HL
ADS
SBC @HL
Btstz
Bitr
Binary Code Summary
SCF RCF CCF
First Byte Condition
PC13-8 ← SP + 1 SP
Ra,#im Ra ← im RR,#imm RR ← imm
EA,RR EA ← EA XOR RR
EA,RR EA ← EA and RR
EA,RR EA ← EA or RR
← a + HL + C
Skip if C =
Second Byte Bit Addresses
FB0H-FBFH FF0H-FFFH
LDB
Instruction Descriptions
ADC Add With Carry
ADC
Operation Operand Operation Summary Bytes Cycles
Operand Binary Code Operation Notation
#8H ← 8H
ADS Add And Skip On Overflow
ADS
ADS EA,HL
JPS YYY
EA ← 0C3H + 12H = 0D5H
Logical
Band Bit Logical
Band
SMB Band
Band C,P1.@L
Flag EQU
Band @H+FLAG
Bitr Bit Reset
Bitr
FF1H-FF9H
Bitr P2.0
BP2 Bitr
Incs BP2
Bits P2.0
Bits Bit Set
Bits
BP2 Bits
BOR Bit Logical or
BOR
BOR @H+FLAG
Btsf Bit Test and Skip on False
Btsf
LABEL2
LABEL3
BP2 Btsf
RET Incs BP2
Btst Bit Test and Skip on True
Btst
BP2 Btst
BP2 Btstz
Btstz Bit Test and Skip on True Clear Bit
Btstz
Btstz @H+FLAG
Bits @H+FLAG
RCF Bxor C,P1.0
Bxor Bit Exclusive or
Bxor
Bxor @H+FLAG
Operand Operation Summary Bytes Cycles
Call Call Procedure
Call Operation
Calls Call Procedure Short
Calls Operation
Calls Play
0FFH 0FEH EMB, ERB 0FDH 0FCH 0FBH 0FAH
CCF Complement Carry Flag
CCF
COM a
COM Complement Accumulator
COM
Cpse EA,HL RET
Cpse Compare and Skip if Equal
Cpse
Decs Decrement and Skip on Borrow
Decs
Decs HL
Call PLAY1
DI Disable Interrupts
EI Enable Interrupts
Idle NOP
Idle Idle Operation
Idle
Incs @HL
Incs Increment and Skip on Carry
Incs
Iret Return From Interrupt
Iret
IS1 IS0 EMB ERB
SC2 SC1 SC0
JP Jump
JP Operation
ADR14
Jump to direct address 14 bits
JPS Jump Short
JPS Operation
ADR12
Jump direct in page 12 bits
JR Jump Relative Very Short
JR KK
JPS AAA BBB CCC DDD
EA,WX ADS WX,EA
JPS YYY XXX LD
LD Load
Description Operand Binary Code Operation Notation
Instruction Operation Description and Guidelines
Examples Instruction Operation Description and Guidelines
LDB Load Bit
LDB
Flag
LDB @H+FLAG
Flag EQU 20H.3 RCF
LDB @H+FLAG,C
LDC Load Code Byte
LDC
Call Display JPS Main ORG
Display LDC
01FFH LDC
Display LD
ORG 01FDH
LDD Load Data Memory and Decrement
LDD Operation
HL,#2FH LDI @HL
LDI Load Data Memory and Increment
LDI Operation
Stop NOP
NOP No Operation
NOP
Or Logical or
Or EA,@HL
POP HL
POP Pop From Stack
POP
Push HL
Push Push Onto Stack
Push
RCF Reset Carry Flag
RCF
Operand Operation Summary Bytes Cycles Memc Reference code
REF Reference Instruction
Operation
AAA LD
BBB EA,#FFH CCC Tcall SUB1 DDD TJP SUB2
BBB EA,#FFH CCC Call SUB1 DDD SUB2
Opcode Symbol Instruction
HL,#0FH
Tcall SUB1
TJP SUB2 ORG
PSW ← EMB,ERB
RET Return From Subroutine
RET
RRC a
RRC Rotate Accumulator Right Through Carry
RRC
SBC Subtract With Carry
SBC
SCF SBC EA,HL
RCF SBC EA,HL
#8H
SBS Subtract
SBS
RCF SBS EA,HL
SCF SBS EA,HL
SCF Set Carry Flag
SCF
SMB Select Memory Bank
SMB
Addresses Register Areas Bank
Format Binary Code Operation Notation
SRB
ERB Setting SRB Settings Selected Register Bank
SRB Select Register Bank
Sret Return From Subroutine and Skip
Sret
Stop Stop Operation
Stop
Vent Load EMB, ERB, and Vector Address
VENTn
VENTn Example The instruction sequence
XCH EA,@HL
XCH Exchange a or EA with Nibble or Byte
XCH
YYY Xchd @HL
Xchd Exchange and Decrement
Xchd Operation
Xchi Exchange and Increment
Xchi Operation
HL,#2FH
YYY Xchi @HL
XOR EA,HL
XOR Logical Exclusive or
XOR
SAM47 Instruction SET
Oscillator Circuits Interrupts Power-Down
Page
Oscillator Circuits
CPU Clock Notation
Using a Subsystem Clock
Clock Control Registers
Clock Circuit Diagram
STO
Main System Oscillator Circuits
Subsystem Oscillator Circuits
Power Control Register Pcon
Pcon Bit Settings Resulting CPU Operating Mode
PCON.1 PCON.0
SCMOD.0 =
Instruction Cycle Times
+ Programming TIP Setting the CPU Clock
PCON,A
System Clock Mode Register Scmod
FB7H SCMOD.3 SCMOD.2 SCMOD.0 Scmod
SCMOD.3 SCMOD.2 SCMOD.0
Fx Oscillation Fxt Oscillation
Oscillator CIRCUITSKS57C2308/P2308/C2316/P2316
KS57C2308/P2308/C2316/P2316OSCILLATOR Circuits
Switching the CPU Clock
Elapsed Machine Cycles During CPU Clock Switch
Clock Output Mode Register Clmod
Result of CLMOD.3 Setting
CLMOD.1 CLMOD.0
Clock Source Frequency
Clock Output Procedure
Clock Output Circuit
CLMOD,A
+ Programming TIP CPU Clock Output to the CLO Pin
PMG2,EA
Interrupt Types and Corresponding Port Pins Interrupt Name
Interrupts
INT0, INT1, INT4
INTB, INTT0, Ints
Power-Down Mode Release
Vectored Interrupts
Software-Generated Interrupts
Multiple Interrupts
Interrupt Execution Flowchart
Interrupt Control Circuit Diagram
Multiple Interrupts
Two-Level Interrupt Handling
Multi-Level Interrupt Handling
Standard Interrupt Priorities Default Priority
Interrupt Priority Register Settings
Result of IPR Bit Setting
Interrupt Priority Register IPR
IMOD0 IMOD0.3 IMOD0.1 IMOD0.0
IMOD1 IMOD1.0
External INTERRUPT0 and INTERRUPT1 Mode Registers
INT0 Noise Filter Edge Clock Selector
INT1 IMOD0
IRQ0 IRQ1 Edge IMOD1
External Interrupt 2 Mode Register IMOD2
IMOD2 Register Bit Settings
Effect of IMOD2 Settings
FB6H IMOD2.2 IMOD2.1 IMOD2.0
Circuit Diagram for INT2 and KS0-KS7 Pins
Interrupt Flags
IME IPR.2 IPR.1 IPR.0
Interrupt Request Flags IRQx
Iret INT4 Bitr IRQ4
+ Programming TIP Enabling the Intb and INT4 Interrupts
Intb Btstz Irqb
POWER-DOWN
Stop Idle
CPU
Idle Mode Timing Diagrams
Timing When Idle Mode is Released by Reset
Stop Mode Timing Diagrams
Timing When Stop Mode is Released by Reset
Keyclk Call MA2SUB
P2,EA
IMOD2,A
SMB Bitr Irqw IRQ2 Bits IEW IE2 CLKS1 Call Watdis
Port PIN Configuration for POWER-DOWN
Recommended Connections for Unused Pins
P3.1/LCDSY
P3.0/LCDCK
SEG0-SEG23
POWER-DOWN
Timing for Oscillation Stabilization After Reset
Hardware Register Values After Reset
Program Status Word PSW
Data Memory RAM
Clocks
Basic Timer
Timer/Counters 0
Watchdog Timer
LCD Driver/Controller
KS57C2308/P2308/C2316/P2316
Port Mode Flags
Pull-Up Resistor Mode Register Pumod
Channel Open-Drain Mode Register PNE
10 I/O Ports
P6,EA
Pumod ID
Port Mode Flags PM Flags
PULL-UP Resistor Mode Register Pumod
Channel OPEN-DRAIN Mode Register PNE
LMOD.7 and LMOD.6 Setting for Port 8 Output Control
LCD Output Segments Bit Output Pins
PIN Addressing for Output Port
SEG24
SEG25
1FAH SEG26
1FBH SEG27
Port 0 Circuit Diagram
Port 0 Circuit Diagram
Port 1 Circuit Diagram
IMOD0 IMOD1
Port 2 Circuit Diagram
Port 2 Circuit Diagram
Port 3 and 6 Circuit Diagram
Port 3 and 6 Circuit Diagram
Port 4 and 5 Circuit Diagram
Port 4 and 5 Circuit Diagram
Port 7 Circuit Diagram
Port 7 Circuit Diagram
10-12
KS57C2308/P2308/C2316/P2316 Timers and TIMER/COUNTERS
Oscillation Stabilization Interval Control
Interval Timer Function
Watchdog Timer Function
Basic Timer Register Overview Type Description Size
Addressing Reset Name Mode
RAM
Wdtcf
Basic Timer Mode Register Bmod
Basic Timer Mode Register Bmod Organization
Basic Timer Input Clock Interval Time
BMOD.3
Basic Timer Counter Bcnt
Basic Timer Operation Sequence
+ Programming TIP Using the Basic Timer
Watchdog Timer Mode Register Wdmod
Watchdog Timer Counter Wdcnt
Watchdog Timer Counter Clear Flag Wdtcf
Bmod
BMOD,A Main Bits Wdtcf
+ Programming TIP Using the Watchdog Timer
Reset Bits EMB SMB
BIT TIMER/COUNTER 0 TC0
TC0 Function Summary
TC0 Component Summary
TC0 Circuit Diagram
TC0 Register Overview Type Description Size
Disable Timer/Counter
TC0 ENABLE/DISABLE Procedure
Enable Timer/Counter
TC0 Programmable TIMER/COUNTER Function
TC0 Operation Sequence
TMOD0 Settings for TCL0 Edge Detection
TC0 Event Counter Function
TMOD0.5 TMOD0.4
TCL0 Edge Detection
+ Programming TIP TC0 Signal Output to the TCLO0 Pin
TC0 Clock Frequency Output
TREF0,EA EA,#4CH TMOD0,EA
Bits TOE0
TREF0,EA EA,#0CH TMOD0,EA
TC0 External Input Signal Divider
TC0 Serial I/O Clock Generation
TC0 Mode Register TMOD0
TMOD0.6, TMOD0.5, and TMOD0.4 Bit Settings
TMOD0.6 TMOD0.5 TMOD0.4
Resulting Counter Source and Clock Frequency
+ Programming TIP Restarting TC0 Counting Operation
TC0 Timing Diagram
TC0 Counter Register TCNT0
TC0 Output Enable Flag TOE0
TC0 Reference Register TREF0
MSB LSB
TC0 Output Latch TOL0
+ Programming TIP Setting a TC0 Timer Interval
TREF0,EA
Clock Source Generation for LCD Controller
Using a System or Subsystem Clock Source
Real-Time and Watch-Time Measurement
Buzzer Output Frequency Generator
Timing Tests in High-Speed Mode
Check Subsystem Clock Level Feature
Watch Timer Circuit Diagram
Watch Timer Mode Register Wmod
Clock Btstz Irqw
+ Programming TIP Using the Watch Timer
WMOD,EA Bits IEW
LCD CONTROLLER/DRIVER
Data BUS LCD Controller Driver
LCD Circuit Diagram
LCD Circuit Diagram
LCD RAM Address Area
LCON.0 and LMOD.3 Bit Settings
LCD Control Register Lcon
LCON.0 LMOD.3 COM0-COM3 SEG0-SEG31
P8.0-P8.7
LMOD.3 LMOD.2 LMOD.1 LMOD.0
LCD Mode Register Lmod
LMOD.5 LMOD.4
LCD Power Supply Static Mode Bias
LCD Drive Voltage
GND
LCD Voltage Dividing Resistors
Voltage Dividing Resistor Circuit Diagrams
Common COM Signals
LCD Common Signal Waveform Static
LCD Common Signal Waveform at 1/2 Bias 1/2, 1/3 Duty
LCD Common Signal Waveform at 1/3 Bias 1/3, 1/4 Duty
Segment SEG Signals
Select/No-Select Signals for LCD Static Display Mode
SEG
Select No-select
Select/No-Select Signals for LCD 1/2 Bias Display Mode
Select Non-select
Select/No-Select Signals for LCD 1/3 Bias Display Mode
10. Select/No-select Bias Signals in 1/3 Bias Display Mode
11. LCD Signal Waveforms in Static Mode
COM0 SEG11 SEG12 VLC0 VSS +VLCD 0 Vlcd
12. LCD Connection Example in Static Mode
13. LCD Signal Waveforms at 1/2 Duty, 1/2 Bias
COM0 COM1 SEG9
14. LCD Connection Example at 1/2 Duty, 1/2 Bias
15. LCD Signal Waveforms at 1/3 Duty, 1/2 Bias
COM0 COM1 COM2 SEG12
16. LCD Connection Example at 1/3 Duty, 1/2 Bias
17. LCD Signal Waveforms at 1/3 Duty, 1/3 Bias
18. LCD Connection Example at 1/3 Duty, 1/3 Bias
19. LCD Signal Waveforms at 1/4 Duty, 1/3 Bias
COM0 COM1 COM2 COM3 SEG13
20. LCD Connection Example at 1/4 Duty, 1/3 Bias
12-24
Serial I/O Interface
Serial I/O Operation Sequence
Serial I/O Interface Circuit Diagram
Serial I/O Mode Register Smod
SMOD.0
SMOD.1
SMOD.2
Serial I/O Timing Diagrams
SIO Timing in Transmit/Receive Mode
Serial I/O Buffer Register Sbuf
SBUF,EA EA,#0EEH SMOD,EA
Bitr EMB EA,TDATA
SBUF,EA EA,#4FH SMOD,EA
SBUF,EA EA,#8FH SMOD,EA
Bits IES Ints Push
XCH EA,SBUF
Bits SMOD.3
SBUF,EA EA,#0FH SMOD,EA
High Speed SIO Transmission
13-8
Standard Electrical Characteristics
Stop Mode Characteristics and Timing Waveforms
Electrical Data
Miscellaneous Timing Waveforms
Parameter Symbol Conditions Rating Units
D.C. Electrical Characteristics
Parameter Symbol Conditions Min Typ Max Units
Absolute Maximum Ratings
Output low
D.C. Electrical Characteristics Concluded
Stop mode DD = 5 V ± 10% CPU = fx/4, Scmod = 0100B
Main System Clock Oscillator Characteristics
Input/Output Capacitance
Subsystem Clock Oscillator Characteristics
Parameter Symbol Condition Min Typ Max Units
A.C. Electrical Characteristics
Input Width
Parameter Symbol Conditions Min Typ Max Unit
Released by Reset 17/fx Time Released by interrupt
Timing Waveforms
A.C. Timing Measurement Points Except for XIN and Xtin
TCL0 Timing
10. Serial Data Transfer Timing
QFP-1420C Package Dimensions
Mechanical Data
15-2
16 KS57P2308/P2316 OTP
KS57P2308/KS57P2316
Test
Operating Mode Characteristics
REG
16-4
16-5
KS57P2308/P2316 OTPKS57C2308/P2308/C2316/P2316
16-7
16-8
16-9
16-10
Timing Waveforms
16-12
16-13
11. Serial Data Transfer Timing
12. OTP Programming Algorithm
KS57P2308/P2316 OTP KS57C2308/P2308/C2316/P2316 16-16
Shine
Sama Assembler
SASM57
HEX2ROM
Smds Product Configuration SMDS2+ 17-2
TB572308A/16A Target Board
Xtal MDS
SMDS2/SMDS2+
Stop LED
XTI
Idle LED
Pin Connectors for TB572308A/16A
DIP
KS57 Series Mask ROM Order Form
Page
KS57 Series Request for Production AT Customer Risk
Risk Order Information
Customer Risk Order Agreement
Order Quantity and Delivery Schedule
Page
KS57C2308 Mask Option Selection Form
Attachment Check one
Prom
Customer Checksum Company Name Signature Engineer
Page
KS57C2316 Mask Option Selection Form
+ What is the purpose of this order?
KS57 Series OTP Factory Writing Order Form 1/2
Page
KS57P2308 OTP Factory Writing Order Form 2/2
Device Number
+ Are you going to continue ordering this device?
If so, how much will you be ordering? PCS
Page
KS57P2316 OTP Factory Writing Order Form 2/2