OSCILLATOR CIRCUITS KS57C2308/P2308/C2316/P2316
6-12
CLOCK OUTPUT MODE REGISTER (CLMOD)
The clock output mode register, CLMOD, is a 4-bit register that is used to enable or disable clock output to the
CLO pin and to select the CPU clock source and frequency. CLMOD is addressable by 4-bit write instructions
only.
FD0HCLMOD.3 "0" CLMOD.1 CLMOD.0 CLMOD
RESET clears CLMOD to logic zero, which automatically selects the CPU clock as the clock source (without
initiating clock oscillation), and disables clock output.
CLMOD.3 is the enable/disable clock output control bit; CLMOD.1 and CLMOD.0 are used to select one of four
possible clock sources and frequencies: normal CPU clock, fxx/8, fxx/16, or fxx/64.
Table 6-7. Clock Output Mode Register (CLMOD) Organization
CLMOD Bit Settings Resulting Clock Output
CLMOD.1 CLMOD.0 Clock Source Frequency
0 0 CPU clock (fx/4, fx/8, fx/64, fxt/4) 1.05 MHz, 524 kHz, 65.5 kHz
0 1 fxx/8 524 kHz
1 0 fxx/16 262 kHz
1 1 fxx/64 65.5 kHz
CLMOD.3 Result of CLMOD.3 Setting
0Clock output is disabled
1Clock output is enabled
NOTE:Assumes that fxx = 4.19 MHz.