ELECTRICAL DATA KS57C2308/P2308/C2316/P2316
14-8
CPU CLOCK = 1/n x oscillator frequency (n = 4, 8, 64)
1
Supply Voltage (V)
250 kHz
500 kHz
750 kHz
1.00 MHz
1.0475 MHz
15.6 kHz
CPU Clock
1.5 MHz
3 4 5 6 7 1.8
Main OSC. Frequency
6 MHz
4.19 MHz
3 MHz
Figure 14-1. Standard Operating Voltage Range
Table 14-7. RAM Data Retention Supply Voltage in Stop Mode
(TA = – 40 °C to + 85 °C)
Parameter Symbol Conditions Min Typ Max Unit
Data retention supply voltage VDDDR Normal operation 1.8 –6.5 V
Data retention supply current IDDDR VDDDR = 1.8 V –0.1 10 µA
Release signal set time tSREL Normal operation 0––µs
Oscillator stabilization wait tWAIT Released by RESET –217/fx –ms
time (1) Released by interrupt –(2) –
NOTES:
1. During oscillator stabilization wait time, all CPU operations must be stopped to avoid instability during oscillator
start-up.
2. Use the basic timer mode register (BMOD) interval timer to delay execution of CPU instructions during the wait time.