SAM47 INSTRUCTION SET KS57C2308/P2308/C2316/P2316
5-60
LD — Load
LD dst,src
Operation: Operand Operation Summary Bytes Cycles
A,#im Load 4-bit immediate data to A 1 1
A,@Rra Load indirect data memory contents to A 1 1
A,DA Load direct data memory contents to A 2 2
A,Ra Load register contents to A 2 2
Ra,#im Load 4-bit immediate data to register 2 2
RR,#imm Load 8-bit immediate data to register 2 2
DA,A Load contents of A to direct data memory 2 2
Ra,A Load contents of A to register 2 2
EA,@HL Load indirect data memory contents to EA 2 2
EA,DA Load direct data memory contents to EA 2 2
EA,RRb Load register contents to EA 2 2
@HL,A Load contents of A to indirect data memory 1 1
DA,EA Load contents of EA to data memory 2 2
RRb,EA Load contents of EA to register 2 2
@HL,EA Load contents of EA to indirect data memory 2 2
Description: The contents of the source are loaded into the destination. The source's contents are unaffected.
If an instruction such as “LD A,#im” (LD EA,#imm) or “LD HL,#imm” is written more than two
times in succession, only the first LD will be executed; the other similar instructions that
immediately follow the first LD will be treated like a NOP. This is called the “redundancy effect”
(see examples below).
Operand Binary Code Operation Notation
A,#im 1 0 1 1 d3 d2 d1 d0 A ← im
A,@Rra 10001i2 i1 i0 A ← (RRa)
A,DA 10001100A ← DA
a7 a6 a5 a4 a3 a2 a1 a0
A,Ra 11011101A ← Ra
00001r2 r1 r0
Ra,#im 11011001Ra ← im
d3 d2 d1 d0 1 r2 r1 r0