INTERRUPTS KS57C2308/P2308/C2316/P2316
7-12
INTERRUPT FLAGS
There are three types of interrupt flags: interrupt request and interrupt enable flags that correspond to each
interrupt, the interrupt master enable flag, which enables or disables all interrupt processing.
Interrupt Master Enable Flag (IME)
The interrupt master enable flag, IME, enables or disables all interrupt processing. Therefore, even when an
IRQx flag is set and its corresponding IEx flag is enabled, the interrupt service routine is not executed until the
IME flag is set to logic one.
The IME flag is located in the IPR register (IPR.3). It can be directly be manipulated by EI and DI instructions,
regardless of the current value of the enable memory bank flag (EMB).
Interrupt Enable Flags (IEx)
IEx flags, when set to logical one, enable specific interrupt requests to be serviced. When the interrupt request
flag is set to logical one, an interrupt will not be serviced until its corresponding IEx flag is also enabled.
Interrupt enable flags can be read, written, or tested directly by 1-bit instructions. IEx flags can be addressed
directly at their specific RAM addresses, despite the current value of the enable memory bank (EMB) flag.
Table 7-7. Interrupt Enable and Interrupt Request Flag Addresses
NOTES:
1. IEx refers to all interrupt enable flags.
2. IRQx refers to all interrupt request flags.
3. IEx = 0 is interrupt disable mode.
4. IEx = 1 is interrupt enable mode.
IME IPR.2 IPR.1 IPR.0 Effect of Bit Settings
0Inhibit all interrupts
1Enable all interrupts
Address Bit 3 Bit 2 Bit 1 Bit 0
FB8H IE4 IRQ4 IEB IRQB
FBAH 0 0 IEW IRQW
FBCH 0 0 IET0 IRQT0
FBDH 0 0 IES IRQS
FBEH IE1 IRQ1 IE0 IRQ0
FBFH 0 0 IE2 IRQ2