Samsung KS57C2308 manual Interrupt Request Flags IRQx, Intb

KS57C2308/P2308/C2316/P2316 INTERRUPTS

Interrupt Request Flags (IRQx)

Interrupt request flags are read/write addressable by 1-bit or 4-bit instructions. IRQx flags can be addressed directly at their specific RAM addresses, regardless of the current value of the enable memory bank (EMB) flag.

When a specific IRQx flag is set to logic one, the corresponding interrupt request is generated. The flag is then automatically cleared to logic zero when the interrupt has been serviced. Exceptions are the watch timer interrupt request flags, IRQW, and the external interrupt 2 flag IRQ2, which must be cleared by software after the interrupt service routine has executed. IRQx flags are also used to execute interrupt requests from software. In summary, follow these guidelines for using IRQx flags:

1.IRQx is set to request an interrupt when an interrupt meets the set condition for interrupt generation.

2.IRQx is set to "1" by hardware and then cleared by hardware when the interrupt has been serviced (with the exception of IRQW and IRQ2).

3.When IRQx is set to "1" by software, an interrupt is generated.

When two interrupts share the same service routine start address, interrupt processing may occur in one of two ways:

—When only one interrupt is enabled, the IRQx flag is cleared automatically when the interrupt has been serviced.

—When two interrupts are enabled, the request flag is not automatically cleared so that the user has an opportunity to locate the source of the interrupt request. In this case, the IRQx setting must be cleared manually using a BTSTZ instruction.

Table 7-8. Interrupt Request Flag Conditions and Priorities

Interrupt	Internal /	Pre-condition for IRQx Flag Setting	Interrupt	IRQ Flag
Source	External		Priority	Name
INTB	I	Reference time interval signal from basic	1	IRQB
		timer
INT4	E	Both rising and falling edges detected at INT4	1	IRQ4
INT0	E	Rising or falling edge detected at INT0 pin	2	IRQ0
INT1	E	Rising or falling edge detected at INT1 pin	3	IRQ1
INTS	I	Completion signal for serial transmit-and-	4	IRQS
		receive or receive-only operation
INTT0	I	Signals for TCNT0 and TREF0 registers	5	IRQT0
		match
INT2 (note)	E	Rising edge detected at INT2 or falling edge	–	IRQ2
(KS0–KS7)		detected at KS0–KS7
INTW	I	Time interval of 0.5 s or 3.19 ms	–	IRQW

NOTE: The quasi-interrupt INT2 is only used for testing incoming signals.

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