I/O PORTS KS57C2308/P2308/C2316/P2316
10-2
Table 10-1. I/O Port Overview
Port I/O Pins Pin Names Address Function Description
0I4P0.0–P0.3 FF0H 4-bit input port.
1-bit and 4-bit read and test are possible.
P0.1 and P0.2 are software configurable as
input or output for SCK and SO by SMOD
register.
4-bit pull-up resistors are software assignable.
1I4P1.0–P1.3 FF1H 4-bit input port.
1-bit and 4-bit read and test are possible.
4-bit pull-up resistors are software assignable.
2I/O 4P2.0–P2.3 FF2H 4-bit I/O port.
1-bit and 4-bit read/write and test is possible.
4-bit pull-up resistors are software assignable.
3I/O 4P3.0–P3.3 FF3H 4-bit I/O Port.
1-bit and 4-bit read/write and test are possible.
4-bit pull-up resistors are software assignable.
Each pin is individually software configurable
as input or output.
4, 5 I/O 8P4.0–P4.3
P5.0–P5.3 FF4H
FF5H 4-bit I/O port. Each pin can be set to N-channel
open-drain output, up to 5 volts. 1-, 4-, and 8-
bit read/write/test are possible. Ports 4 and 5
can be paired to support 8-bit data transfer.
Pull-up resistors are software assignable; pull-
up resistor are automatically disable for output.
6, 7 I/O 8P6.0–P6.3
P7.0–P7.3 FF6H
FF7H 4-bit I/O port. Port 6 pins are individually
software configurable as input or output. 1-,
and 4-bit read/write/test are possible. 4-bit
pull-up resistors are software assignable. Ports
6 and 7 can be paired for 8-bit data transfer.
8O8P8.0–P8.7 1F8H–1FFH Output port for 1-bit data (for use as CMOS
driver only)
Table 10-2. Port Pin Status During Instruction Execution
Instruction Type Example Input Mode Status Output Mode Status
1-bit test
1-bit input
4-bit input
8-bit input
BTST
LDB
LD
LD
P0.1
C,P1.3
A,P0
EA,P4
Input or test data at each pin Input or test data at output latch
1-bit output BITR P2.3 Output latch contents undefined Output pin status is modified
4-bit output
8-bit output LD
LD P2,A
P6,EA Transfer accumulator data to the
output latch Transfer accumulator data to the
output pin