KS57C2308/P2308/C2316/P2316 SAM47 INSTRUCTION SET
5-7
OPCODE DEFINITIONS
Table 5-7. Opcode Definitions (Direct)
Register r2 r1 r0
A000
E001
L 0 1 0
H011
X100
W101
Z110
Y111
EA 000
HL 010
WX 100
YZ 110
r = Immediate data for register
Table 5-8. Opcode Definitions (Indirect)
Register i2 i1 i0
@HL 101
@WX 110
@WL 111
CALCULATING ADDITIONAL MACHINE CYCLES FOR SKIPS
A machine cycle is defined as one cycle of the selected CPU clock. Three different clock rates can be selected
using the PCON register.
In this document, the letter “S” is used in tables when describing the number of additional machine cycles
required for an instruction to execute, given that the instruction has a skip function (“S” = skip). The addition
number of machine cycles that will be required to perform the skip usually depends on the size of the instruction
being skipped — whether it is a 1-byte, 2-byte, or 3-byte instruction. A skip is also executed for SMB and SRB
instructions.
The values in additional machine cycles for “S” for the three cases in which skip conditions occur are as follows:
Case 1:No skip S = 0 cycles
Case 2:Skip is 1-byte or 2-byte instruction S = 1 cycle
Case 3:Skip is 3-byte instruction S = 2 cycles
NOTE:REF instructions are skipped in one machine cycle.
i = Immediate data for indirect addressing