Samsung KS57C2308 manual Interval Timer Function, Oscillation Stabilization Interval Control

TIMERS and TIMER/COUNTERS KS57C2308/P2308/C2316/P2316

BASIC TIMER (BT)

OVERVIEW

The 8-bit basic timer (BT) has five functional components:

—Clock selector logic

—4-bit mode register (BMOD)

—8-bit counter register (BCNT)

—8-bit watchdog timer mode register (WDMOD)

—Watchdog timer counter clear flag (WDTCF)

The basic timer generates interrupt requests at precise intervals, based on the frequency of the system clock. Basic timer’s counter register, BCNT, outputs timer pulses to the watchdog timer’s counter register, WDTCNT when an overflow occurs in BCNT. You can use the basic timer as a "watchdog" timer for monitoring system events or use BT output to stabilize clock oscillation when stop mode is released by an interrupt and following RESET. Bit settings in the basic timer mode register BMOD turns the BT on and off, selects the input clock frequency, and controls interrupt or stabilization intervals.

Interval Timer Function

The measurement of elapsed time intervals is the basic timer's primary function. The standard interval is 256 BT clock pulses.

To restart the basic timer, set bit 3 of the mode register BMOD to logic one. The input clock frequency and the interrupt and stabilization interval are selected by loading the appropriate bit values to BMOD.2–BMOD.0.

The 8-bit counter register, BCNT, is incremented each time a clock signal is detected that corresponds to the frequency selected by BMOD. BCNT continues incrementing as it counts BT clocks until an overflow occurs. An overflow causes the BT interrupt request flag (IRQB) to be set to logic one to signal that the designated time interval has elapsed. An interrupt request is then generated, BCNT is cleared to logic zero, and counting continues from 00H.

Oscillation Stabilization Interval Control

Bits 2–0 of the BMOD register are used to select the input clock frequency for the basic timer. This setting also determines the time interval (also referred to as “wait time”) required to stabilize clock signal oscillation when power-down mode is released by an interrupt. When a RESET signal is generated, the standard stabilization interval for system clock oscillation following a RESET is 31.3 ms at 4.19 MHz.

Watchdog Timer Function

The basic timer can also be used as a “watchdog” timer to detect an inadvertent program loop, that is, system or program operation error. For this purpose, instruction that clears the watchdog timer (BITS WDTCF) within a given period should be executed at proper points in a program. If an instruction that clears the watchdog timer is not done within the period and the watchdog timer overflows, reset signal is generated and system is restarted with reset status. An operation of watchdog timer is as follows:

—Write some value (except #5AH) to Watchdog Timer Mode register, WDMOD.

—Each time BCNT overflows, an overflow signal is sent to the watchdog timer counter, WDCNT.

—If WDTCNT overflows, system reset will be generated.

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