Texas Instruments PCI7611, PCI7411, PCI7621 Bridge Control Register, Interrupt pin, Bridge control

Register:	Interrupt pin
Offset:	3Dh
Type:	Read-only
Default:	01h (function 0), 02h (function 1), 03h (function 2), 04h (function 3), 04h (function 4), 04h
(function 5)

Table 4−6. Interrupt Pin Register Cross Reference

INTRTIE BIT

TIEALL BIT

INTPIN

INTPIN

INTPIN

INTPIN

INTPIN

INTPIN

(BIT 29,

(BIT 28,

FUNCTION 0

FUNCTION 1

FUNCTION 2

FUNCTION 3

FUNCTION 4

FUNCTION 5

OFFSET 80h)

OFFSET 80h)

(CARDBUS)

(CARDBUS)

(1394 OHCI)

(FLASH MEDIA)

(SD HOST)

(SMART CARD)

Determined by

Determined by

Determined by

bits 6−5

bits 6−5

bits 6−5

0

0

01h

(INTA)

02h

(INTB)

03h

(INTC)

(INT_SEL) in the

(INT_SEL) in the

(INT_SEL) in the

flash media

SD host general

Smart Card

general control

control register

general control

1

0

01h

(INTA)

01h

(INTA)

03h

(INTC)

register (see

(see

register (see

Section 11.21)

Section 12.22)

Section 13.22)

X

1

01h

01h

01h

01h

01h

01h

(INTA)

(INTA)

(INTA)

(INTA)

(INTA)

(INTA)

4.25 Bridge Control Register

The bridge control register provides control over various PCI7x21/PCI7x11 bridging functions. Some bits in this register are global in nature and must be accessed only through function 0. See Table 4−7 for a complete description of the register contents.

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

Bridge control

Type

R

R

R

R

R

RW

RW

RW

RW

RW

RW

R

RW

RW

RW

RW

Default

0

0

0

0

0

0

1

1

0

1

0

0

0

0

0

0

Register:

Bridge control

Offset:

3Eh (Function 0, 1)

Type:

Read-only, Read/Write

Default:

0340h

Table 4−7. Bridge Control Register Description

BIT

SIGNAL

TYPE

FUNCTION

15−11

RSVD

R

These bits return 0s when read.

Write posting enable. Enables write posting to and from the CardBus sockets. Write posting enables the

10

POSTEN

RW

posting of write data on burst cycles. Operating with write posting disabled impairs performance on burst

cycles. Note that burst write data can be posted, but various write transactions may not. This bit is socket

dependent and is not shared between functions 0 and 1.

Memory window 1 type. This bit specifies whether or not memory window 1 is prefetchable. This bit is

9

PREFETCH1

RW

socket dependent. This bit is encoded as:

0 = Memory window 1 is nonprefetchable.

1 = Memory window 1 is prefetchable (default).

Memory window 0 type. This bit specifies whether or not memory window 0 is prefetchable. This bit is

8

PREFETCH0

RW

socket dependent. This bit is encoded as:

0 = Memory window 0 is nonprefetchable.

1 = Memory window 0 is prefetchable (default).

PCI interrupt − IREQ routing enable. This bit is used to select whether PC Card functional interrupts are

7

INTR

RW

routed to PCI interrupts or to the IRQ specified in the ExCA registers.

0 = Functional interrupts are routed to PCI interrupts (default).

1 = Functional interrupts are routed by ExCA registers.

4−15