Texas Instruments PCI7411, PCI7611, PCI7621 Socket Present State Register, Socket present state

6.3 Socket Present State Register

This register reports information about the socket interface. Writes to the socket force event register (offset 0Ch, see Section 6.4), as well as general socket interface status, are reflected here. Information about PC Card VCC support and card type is only updated at each insertion. Also note that the PCI7x21/PCI7x11 controller uses the CCD1 and CCD2 signals during card identification, and changes on these signals during this operation are not reflected in this register.

Bit	31	30	29	28	27	26	25		24	23	22	21	20	19	18	17	16
Name								Socket present state
Type	R	R	R	R	R	R	R		R	R	R	R	R	R	R	R	R
Default	0	0	1	1	0	0	0		0	0	0	0	0	0	0	0	0

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Name

Socket present state

Type

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

R

Default

0

0

0

0

0

0

0

0

0

X

0

0

0

X

X

X

Register:

Socket present state

Offset:

CardBus Socket Address + 08h

Type:

Read-only

Default:

3000 00XXh

Table 6−4. Socket Present State Register Description

BIT

SIGNAL

TYPE

FUNCTION

YV socket. This bit indicates whether or not the socket can supply VCC = Y.Y V to PC Cards. The

31

YVSOCKET

R

PCI7x21/PCI7x11 controller does not support Y.Y-V VCC; therefore, this bit is always reset unless

overridden by the socket force event register (offset 0Ch, see Section 6.4). This bit defaults to 0.

XV socket. This bit indicates whether or not the socket can supply VCC = X.X V to PC Cards. The

30

XVSOCKET

R

PCI7x21/PCI7x11 controller does not support X.X-V VCC; therefore, this bit is always reset unless

overridden by the socket force event register (offset 0Ch, see Section 6.4). This bit defaults to 0.

3-V socket. This bit indicates whether or not the socket can supply VCC = 3.3 Vdc to PC Cards. The

29

3VSOCKET

R

PCI7x21/PCI7x11 controller does support 3.3-V VCC; therefore, this bit is always set unless overridden

by the socket force event register (offset 0Ch, see Section 6.4).

5-V socket. This bit indicates whether or not the socket can supply VCC = 5 Vdc to PC Cards. The

28

5VSOCKET

R

PCI7x21/PCI7x11 controller does support 5-V VCC; therefore, this bit is always set unless overridden

by bit 6 of the device control register (PCI offset 92h, see Section 4.39).

27−14

RSVD

R

These bits return 0s when read.

YV card. This bit indicates whether or not the PC Card inserted in the socket supports VCC = Y.Y Vdc.

13 †

YVCARD

R

This bit can be set by writing a 1 to the corresponding bit in the socket force event register (offset 0Ch,

see Section 6.4).

XV card. This bit indicates whether or not the PC Card inserted in the socket supports VCC = X.X Vdc.

12 †

XVCARD

R

This bit can be set by writing a 1 to the corresponding bit in the socket force event register (offset 0Ch,

see Section 6.4).

3-V card. This bit indicates whether or not the PC Card inserted in the socket supports VCC = 3.3 Vdc.

11 †

3VCARD

R

This bit can be set by writing a 1 to the corresponding bit in the socket force event register (offset 0Ch,

see Section 6.4).

5-V card. This bit indicates whether or not the PC Card inserted in the socket supports VCC = 5 Vdc.

10 †

5VCARD

R

This bit can be set by writing a 1 to the corresponding bit in the socket force event register (offset 0Ch,

see Section 6.4).

†One or more bits in the register are PME context bits and can be cleared only by the assertion of GRST when PME is enabled. If PME is not enabled, then these bits are cleared by the assertion of PRST or GRST.

6−4