Table 2−5. PC Card Power Switch Terminals

Internal pullup/pulldown resistors, power rail designation, and pin strapping are not applicable for the power switch terminals.

TERMINAL

DESCRIPTION

I/O

INPUT

OUTPUT

EXTERNAL

NAME

NO.

TYPE

COMPONENTS

 

 

 

 

 

 

 

 

 

 

 

 

Power switch clock. Information on the DATA line is sampled at the rising edge of

 

 

 

PCMCIA power

CLOCK

L06

CLOCK. CLOCK defaults to an input, but can be changed to an output by using bit 27

I/O

TTLI1

TTLO1

switch

 

 

(P2CCLK) in the system control register (offset 80h, see Section 4.29).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DATA

N01

Power switch data. DATA is used to communicate socket power control information

O

 

LVCO1

PCMCIA power

serially to the power switch.

 

switch

 

 

 

 

 

 

 

 

 

 

 

 

LATCH

N02

Power switch latch. LATCH is asserted by the controller to indicate to the power

O

 

LVCO1

PCMCIA power

switch that the data on the DATA line is valid.

 

switch

 

 

 

 

 

 

 

 

 

 

 

 

Table 2−6. PCI System Terminals

Internal pullup/pulldown resistors and pin strapping are not applicable for the PCI terminals.

 

TERMINAL

 

 

DESCRIPTION

I/O

INPUT

POWER

EXTERNAL

 

NAME

NO.

 

 

TYPE

RAIL

COMPONENTS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Global reset. When the global reset is asserted, the

 

 

signal causes the

 

 

 

 

 

 

 

 

 

 

 

GRST

 

 

 

 

 

 

 

 

 

 

 

controller to place all output buffers in a high-impedance state and reset all internal

 

 

 

 

 

 

 

 

 

 

 

registers. When GRST is asserted, the controller is completely in its default state. For

 

 

 

 

 

 

 

 

 

 

 

systems that require wake-up from D3, GRST is normally asserted only during initial

 

 

 

Power-on reset or

 

GRST

T01

boot. PRST must be asserted following initial boot so that PME context is retained

I

LVCI2

 

 

 

 

 

 

 

 

tied to PRST

 

 

 

 

 

when transitioning from D3 to D0. For systems that do not require wake-up from D3,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GRST must be tied to PRST. When the SUSPEND mode is enabled, the controller is

 

 

 

 

 

 

 

 

 

 

 

protected from the

GRST,

and the internal registers are preserved. All outputs are

 

 

 

 

 

 

 

 

 

 

 

placed in a high-impedance state, but the contents of the registers are preserved.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCLK

P05

PCI bus clock. PCLK provides timing for all transactions on the PCI bus. All PCI

I

PCII3

VCCP

 

 

 

 

signals are sampled at the rising edge of PCLK.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCI bus reset. When the PCI bus reset is asserted,

 

 

causes the controller to

 

 

 

 

 

 

 

 

 

 

 

PRST

 

 

 

 

 

 

 

 

 

 

 

place all output buffers in a high-impedance state and reset some internal registers.

 

 

 

 

 

 

 

 

 

 

 

When PRST is asserted, the controller is completely nonfunctional. After PRST is

 

 

 

 

 

 

 

PRST

 

R03

deasserted, the controller is in a default state.

I

PCII3

VCCP

 

 

 

 

 

 

 

 

When SUSPEND and PRST are asserted, the controller is protected from

PRST

 

 

 

 

 

 

 

 

 

 

 

 

clearing the internal registers. All outputs are placed in a high-impedance state, but

 

 

 

 

 

 

 

 

 

 

 

the contents of the registers are preserved.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2−15

Page 41
Image 41
Texas Instruments PCI7611, PCI7411, PCI7621, PCI7421 manual 5. PC Card Power Switch Terminals, 6. PCI System Terminals, 15