Texas Instruments PCI7411 Is enabled and the Smart Card controller has, Tabtsig RCU, Intstat

13.4 Status Register

The status register provides device information to the host system. All bit functions adhere to the definitions in the PCI Local Bus Specification, as seen in the following bit descriptions. Bits in this register may be read normally. A bit in the status register is reset when a 1 is written to that bit location; a 0 written to a bit location has no effect. See Table 13−3 for a complete description of the register contents.

Bit	15	14	13	12	11	10	9	8		7	6	5	4	3	2	1	0
Name									Status
Type	RCU	RCU	R	R	RCU	R	R	R		R	R	R	R	RU	R	R	R
Default	0	0	0	0	0	0	1	0		0	0	0	1	0	0	0	0
	Register:		Status
	Offset:		06h
	Type:		Read/Clear/Update, Read-only
	Default:		0210h

			Table 13−3. Status Register Description
BIT	FIELD NAME	TYPE	DESCRIPTION
15	PAR_ERR	RCU	Detected parity error. Bit 15 is set to 1 when either an address parity or data parity error is detected.
14	SYS_ERR	RCU	Signaled system error. Bit 14 is set to 1 when			is enabled and the Smart Card controller has
				SERR
			signaled a system error to the host.
13	MABORT	R	This function does not support bus mastering. This bit is hardwired to 0.
12	TABT_REC	R	This function does not support bus mastering and never receives a target abort. This bit is hardwired
			to 0.
11	TABT_SIG	RCU	Signaled target abort. Bit 11 is set to 1 by the Smart Card controller when it terminates a transaction
			on the PCI bus with a target abort.
10−9	PCI_SPEED	R	DEVSEL timing. Bits 10 and 9 encode the timing of				and are hardwired to 01b, indicating that
					DEVSEL
			the Smart Card controller asserts this signal at a medium speed on nonconfiguration cycle accesses.
8	DATAPAR	R	This function does not support bus mastering. This bit is hardwired to 0.
7	FBB_CAP	R	Fast back-to-back capable. The Smart Card controller cannot accept fast back-to-back transactions;
			therefore, bit 7 is hardwired to 0.
6	RSVD	R	Reserved. Bit 6 returns 0 when read.
5	66MHZ	R	66-MHz capable. The Smart Card controller operates at a maximum PCLK frequency of 33 MHz;
			therefore, bit 5 is hardwired to 0.
4	CAPLIST	R	Capabilities list. Bit 4 returns 1 when read, indicating that the Smart Card controller supports additional
			PCI capabilities. The linked list of PCI power-management capabilities is implemented in this function.
3	INT_STAT	RU	Interrupt status. This bit reflects the interrupt status of the function. Only when bit 10 (INT_DISABLE)
			in the command register (see Section 11.3) is a 0 and this bit is 1, is the function’s INTx signal asserted.
			Setting the INT_DISABLE bit to 1 has no effect on the state of this bit. This bit is set only when a valid
			interrupt condition exists. This bit is not set when an interrupt condition exists and signaling of that event
			is not enabled.
2−0	RSVD	R	Reserved. Bits 3−0 return 0s when read.

13−4