Table

Title

Page

11−5

Latency Timer and Class Cache Line Size Register Description

. 11−5

11−6

Header Type and BIST Register Description

. 11−6

11−7

Flash Media Base Address Register Description

. 11−6

11−8

PCI Interrupt Pin Register

. 11−8

11−9

Minimum Grant Register Description

. 11−9

11−10

Maximum Latency Register Description

. 11−9

11−11

Capability ID and Next Item Pointer Registers Description

11−10

11−12

Power Management Capabilities Register Description

11−11

11−13

Power Management Control and Status Register Description

11−12

11−14

General Control Register

11−13

11−15

Subsystem Access Register Description

11−14

11−16

Diagnostic Register Description

11−15

12−1

Function 4 Configuration Register Map

. 12−1

12−2

Command Register Description

. 12−3

12−3

Status Register Description

. 12−4

12−4

Class Code and Revision ID Register Description

. 12−5

12−5

Latency Timer and Class Cache Line Size Register Description

. 12−6

12−6

Header Type and BIST Register Description

. 12−6

12−7

SD host Base Address Register Description

. 12−7

12−8

PCI Interrupt Pin Register

. 12−9

12−9

Minimum Grant Register Description

. 12−9

12−10

Maximum Latency Register Description

12−10

12−11

Maximum Latency Register Description

12−10

12−12

Capability ID and Next Item Pointer Registers Description

12−11

12−13

Power Management Capabilities Register Description

12−12

12−14

Power Management Control and Status Register Description

12−13

12−15

General Control Register

12−14

12−16

Subsystem Access Register Description

12−15

12−17

Diagnostic Register Description

12−15

13−1

Function 5 Configuration Register Map

. 13−1

13−2

Command Register Description

. 13−3

13−3

Status Register Description

. 13−4

13−4

Class Code and Revision ID Register Description

. 13−5

13−5

Latency Timer and Class Cache Line Size Register Description

. 13−5

13−6

Header Type and BIST Register Description

. 13−6

13−7

PCI Interrupt Pin Register

. 13−9

13−8

Minimum Grant Register Description

. 13−9

13−9

Maximum Latency Register Description

13−10

13−10

Capability ID and Next Item Pointer Registers Description

13−10

13−11

Power Management Capabilities Register Description

13−11

13−12

Power Management Control and Status Register Description

13−12

13−13

General Control Register

13−13

13−14

Subsystem ID Alias Register Description

13−14

xvii

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Texas Instruments PCI7611, PCI7411, PCI7621, PCI7421 manual Xvii