Texas Instruments PCI7411, PCI7611, PCI7621, PCI7421 manual 4. Power Supply Terminals, 14

Table 2−4. Power Supply Terminals

Output description, internal pullup/pulldown resistors, and the power rail designation are not applicable for the power supply terminals.

	TERMINAL		DESCRIPTION	I/O	INPUT	EXTERNAL	PIN STRAPPING
NAME		NUMBER		TYPE		COMPONENTS	(IF UNUSED)
AGND		N12, U14,	Analog circuit ground terminals	GND			NA
		U16
			Analog circuit power terminals. A parallel combination of high
			frequency decoupling capacitors near each terminal is suggested,			0.1-∝F, 0.001-∝F,
			such as 0.1 ∝F and 0.001 ∝F. Lower frequency 10-∝F filtering
		R13, R14,				and 10-∝F
AVDD			capacitors are also recommended. These supply terminals are	GND			NA
		V17				capacitors tied to
			separated from VDPLL_33 internal to the controller to provide
						AGND
			noise isolation. They must be tied to a low-impedance point on the
			circuit board.
		G07, G08,
		G13, H13,
		J09, J10,
GND		J11, K09,	Digital ground terminal	GND			NA
		K10, K11,
		L08, L09,
		L10, L11,
		L12, M08
		H08, H09,
		H10, H11,
		H12, J08,
VCC		J12, K08,	Power supply terminal for I/O and internal voltage regulator	PWR			NA
		K12, M07,
		M09, M10,
		M12, N07
VCCA		A05, A11	Clamp voltage for PC Card A interface. Matches card A signaling	PWR			Float
			environment, 5 V or 3.3 V
VCCB		D19, K19	Clamp voltage for PC Card B interface. Matches card B signaling	PWR			Float
			environment, 5 V or 3.3 V
VCCP		W03, W10	Clamp voltage for PCI and miscellaneous I/O, 5 V or 3.3 V	PWR			NA
			1.5-V PLL circuit power terminal. An external capacitor (0.1 ∝F
			recommended) must be placed between terminals T18 and T17
			(VSSPLL) when the internal voltage regulator is enabled			0.1-∝F, 0.001-∝F,
VDPLL_15		T18	(VR_EN = 0 V). When the internal voltage regulator is disabled,			and 10-∝F	NA
			1.5-V must be supplied to this terminal and a parallel combination			capacitors tied to
			of high frequency decoupling capacitors near the terminal is			VSPLL
			suggested, such as 0.1 ∝F and 0.001 ∝F. Lower frequency 10-∝F
			filtering capacitors are also recommended.
			3.3-V PLL circuit power terminal. A parallel combination of high
			frequency decoupling capacitors near the terminal is suggested,
			such as 0.1 ∝F and 0.001 ∝F. Lower frequency 10-∝F filtering			0.1-∝F, 0.001-∝F,
			capacitors are also recommended. This supply terminal is
						and 10-∝F
VDPLL_33		V19	separated from AVDD internal to the controller to provide noise	PWR			NA
						capacitors tied to
			isolation. It must be tied to a low-impedance point on the circuit
						VSPLL
			board. When the internal voltage regulator is disabled
			(VR_EN = 3.3 V), no voltage is required to be supplied to this
			terminal.
						Pulled directly to
VR_EN		H02	Internal voltage regulator enable. Active low	FT	FT		NA
						GND
VR_PORT		H01, M19	1.5-V output from the internal voltage regulator	PWR		0.1-∝F capacitor	NA
						tied to GND
VSSPLL		P14, T17	PLL circuit ground terminal. This terminal must be tied to the	GND			NA
			low-impedance circuit board ground plane.

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