Texas Instruments PCI7621, PCI7411, PCI7611 11 -Bit PC Card Interface Control Terminals, Stschg

Table 2−11. 16-Bit PC Card Interface Control Terminals

External components are not applicable for the 16-bit PC Card interface control terminals. If any 16-bit PC Card interface control terminal is unused, then the terminal may be left floating.

SKT A TERMINAL

SKT B TERMINAL†

DESCRIPTION

I/O

POWER

NAME

NO.

NAME

NO.

TYPE

RAIL

Battery voltage detect 1. BVD1 is generated by 16-bit memory PC Cards that

include batteries. BVD1 is used with BVD2 as an indication of the condition of the

batteries on a memory PC Card. Both BVD1 and BVD2 are high when the battery

is good. When BVD2 is low and BVD1 is high, the battery is weak and must be

replaced. When BVD1 is low, the battery is no longer serviceable and the data in

A_BVD1

B02

B_BVD1

F14

the memory PC Card is lost. See Section 5.6, ExCA Card Status-Change Interrupt

I

VCCA/

Configuration Register, for enable bits. See Section 5.5, ExCA Card

(STSCHG/RI)

(STSCHG/RI)

VCCB

Status-Change Register, and Section 5.2, ExCA Interface Status Register, for the

status bits for this signal.

Status change.

STSCHG

alerts the system to a change in the READY, write

protect, or battery voltage dead condition of a 16-bit I/O PC Card.

Ring indicate.

RI

is used by 16-bit modem cards to indicate a ring detection.

Battery voltage detect 2. BVD2 is generated by 16-bit memory PC Cards that

include batteries. BVD2 is used with BVD1 as an indication of the condition of the

batteries on a memory PC Card. Both BVD1 and BVD2 are high when the battery

is good. When BVD2 is low and BVD1 is high, the battery is weak and must be

replaced. When BVD1 is low, the battery is no longer serviceable and the data in

the memory PC Card is lost. See Section 5.6, ExCA Card Status-Change Interrupt

A_BVD2

B_BVD2

Configuration Register, for enable bits. See Section 5.5, ExCA Card

VCCA/

A02

C17

Status-Change Register, and Section 5.2, ExCA Interface Status Register, for the

I

VCCB

(SPKR)

(SPKR)

status bits for this signal.

Speaker.

SPKR

is an optional binary audio signal available only when the card and

socket have been configured for the 16-bit I/O interface. The audio signals from

cards A and B are combined by the controller and are output on SPKROUT.

DMA request. BVD2 can be used as the DMA request signal during DMA

operations to a 16-bit PC Card that supports DMA. The PC Card asserts BVD2 to

indicate a request for a DMA operation.

Card detect 1 and card detect 2.

and

are internally connected to ground

C15

N13

CD1

CD2

A_CD1

B_CD1

on the PC Card. When a PC Card is inserted into a socket, CD1 and CD2 are

I

A_CD2

E05

B_CD2

B17

pulled low. For signal status, see Section 5.2, ExCA Interface Status Register.

Card enable 1 and card enable 2.

and

enable even- and odd-numbered

G12

M18

CE1

CE2

VCCA/

A_CE1

B_CE1

address bytes. CE1 enables even-numbered address bytes, and CE2 enables

O

A_CE2

B12

B_CE2

L19

VCCB

odd-numbered address bytes.

Input acknowledge.

is asserted by the PC Card when it can respond to an

INPACK

I/O read cycle at the current address.

VCCA/

A_INPACK

E07

B_INPACK

E18

DMA request. INPACK can be used as the DMA request signal during DMA

I

VCCB

operations from a 16-bit PC Card that supports DMA. If it is used as a strobe, then

the PC Card asserts this signal to indicate a request for a DMA operation.

I/O read.

is asserted by the controller to enable 16-bit I/O PC Card data

IORD

output during host I/O read cycles.

VCCA/

A_IORD

C11

B_IORD

L15

DMA write. IORD is used as the DMA write strobe during DMA operations from a

O

VCCB

16-bit PC Card that supports DMA. The controller asserts IORD during DMA

transfers from the PC Card to host memory.

I/O write.

is driven low by the controller to strobe write data into 16-bit I/O

IOWR

PC Cards during host I/O write cycles.

VCCA/

A_IOWR

E11

B_IOWR

L13

DMA read. IOWR is used as the DMA write strobe during DMA operations from a

O

VCCB

16-bit PC Card that supports DMA. The controller asserts IOWR during transfers

from host memory to the PC Card.

†These terminals are reserved for the PCI7611 and PCI7411 controllers.

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